ADS8319
- 500-kHz Sample Rate
- 16-Bit Resolution
- Zero Latency at Full Speed
- Unipolar, Single-Ended Input Range: 0 V to VREF
- SPI-Compatible Serial Interface With Daisy-Chain Option
- Excellent Performance:
- 93.6-dB SNR (Typical) at 10-kHz Input
- –106-dB THD (Typical) at 10-kHz Input
- ±1.5-LSB (Maximum) INL
- ±1-LSB (Maximum) DNL
- Low Power Dissipation: 18 mW (Typical) at 500 kSPS
- Power Scales Linearly with Speed: 3.6 mW / 100 kSPS
- Power Dissipation During Power-Down State: 0.25 µW (Typical)
- 10-Pin VSSOP and VSON Packages
The ADS8319 device is a 16-bit, 500-kSPS, analog-to-digital converter (ADC) that operates with a 2.25-V to 5.5-V external reference. The device includes a capacitor-based, successive-approximation register (SAR) ADC with inherent sample and hold.
The device includes a 50-MHz, SPI-compatible serial interface. The interface is designed to support daisy-chaining or cascading of multiple devices. Furthermore, a Busy Indicator makes synchronizing with the digital host easy.
The device unipolar, single-ended input range supports an input swing of 0 V to +VREF.
Device operation is optimized for very-low power operation and the power consumption directly scales with speed. This feature makes the device attractive for lower-speed applications. The device is available in 10-pin VSSOP and VSON packages.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | ADS8319 16-Bit, 500-kSPS, Serial Interface, Micropower, Miniature, SAR Analog-to-Digital Converter datasheet (Rev. C) | PDF | HTML | 2016/12/9 | ||
| Circuit design | Antialiasing filter circuit design for single-ended ADC input using fixed cutoff (Rev. B) | PDF | HTML | 2024/9/24 | |||
| Circuit design | Circuit for protecting low-voltage SAR ADC from electrical overstress with minim (Rev. A) | PDF | HTML | 2024/9/19 | |||
| 白皮書 | Voltage-reference impact on total harmonic distortion | 2016/8/1 | ||||
| 更多文件說明 | SAR ADCs for PLC Applications | PDF | HTML | 2016/2/11 | |||
| 電子書 | Best of Baker's Best: Precision Data Converters -- SAR ADCs | 2015/5/21 | ||||
| 應用說明 | Determining Minimum Acquisition Times for SAR ADCs, part 2 | 2011/3/17 | ||||
| 類比設計期刊 | The IBIS model, Part 2: Determining the total quality of an IBIS model | 2011/3/14 | ||||
| 應用說明 | Determining Minimum Acquisition Times for SAR ADCs, part 1 (Rev. A) | 2010/11/10 | ||||
| 應用說明 | Low Power Input and Reference Driver Circuit for ADS8318 and ADS8319 | 2009/6/24 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
SBAC197 — Source Files for SBAA282
ANALOG-ENGINEER-CALC — PC software analog engineer's calculator
類比工程師的計算機旨在加速類比電路設計工程師定期使用的許多重複計算。此基於 PC 的工具提供圖形介面，列出各種常見計算，從使用回饋電阻器設定運算放大器增益到選擇適當的電路設計元件以穩定類比數位轉換器 (ADC) 驅動緩衝電路。
除了作為獨立工具使用外，此計算機還與類比工程師口袋參考中描述的概念相得益彰。
JITTER-SNR-CALC — Jitter and SNR calculator
JITTER-SNR-CALC can be used for calculating theoretical Signal to Noise (SNR) performance of ADCs based on input frequency and clock jitter.
ADC-DAC-TO-VREF-SELECT-DESIGN-TOOL — The ADC-TO-VREF-SELECT tool enables the pairing of TI ADCs, DACs, and series voltage references.
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VSSOP (DGS) | 10 | Ultra Librarian |
| VSON (DRC) | 10 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。