ADS1602
- High Speed:
- Data Rate: 2.5MSPS
- Bandwidth: 1.23MHz
- Outstanding Performance:
- SNR: 91dB at fIN = 100kHz, –1dBFS
- THD: –101dB at fIN = 100kHz, –6dBFS
- SFDR: 103dB at fIN = 100kHz, –6dBFS
- Ease-of-Use:
- High-Speed 3-Wire Serial Interface
- Directly Connects to TMS320 DSPs
- On-Chip Digital Filter Simplifies Antialias Requirements
- Simple Pin-Driven Control—No On-Chip Registers to Program
- Selectable On-Chip Voltage Reference
- Simultaneous Sampling with Multiple ADS1602s
- Low Power:
- 530mW at 2.5MSPS
- Power-Down Mode
The ADS1602 is a high-speed, high-precision, delta-sigma (ΔΣ) analog-to-digital converter (ADC) manufactured on an advanced CMOS process. The ADS1602 oversampling topology reduces clock jitter sensitivity during the sampling of high-frequency, large amplitude signals by a factor of four over that achieved by Nyquist-rate ADCs. Consequently, signal-to-noise ratio (SNR) is particularly improved. Total harmonic distortion (THD) is –101dB, and the spurious-free dynamic range (SFDR) is 103dB.
Optimized for power and performance, the ADS1602 dissipates only 530mW while providing a full-scale differential input range of ±3V. Having such a wide input range makes out-of-range signals unlikely. The OTR pin indicates if an analog input out-of-range condition does occur. The differential input signal is measured against the differential reference, which can be generated internally or supplied externally on the ADS1602.
The ADS1602 uses an inherently stable advanced modulator with an on-chip decimation filter. The filter stop band extends to 38.6MHz, which greatly simplifies the antialiasing circuitry. The modulator samples the input signal up to 40MSPS, depending on fCLK, while the 16x decimation filter uses a series of four half-band FIR filter stages to provide 75dB of stop band attenuation and 0.001dB of passband ripple.
Output data is provided over a simple 3-wire serial interface at rates up to 2.5MSPS, with a –3dB bandwidth of 1.23MHz. The output data or its complementary format directly connects to DSPs such as TI’s TMS320 family, FPGAs, or ASICs. A dedicated synchronization pin enables simultaneous sampling with multiple ADS1602s in multi-channel systems. Power dissipation is set by an external resistor that allows a reduction in dissipation when operating at slower speeds. All of the ADS1602 features are controlled by dedicated I/O pins, which simplify operation by eliminating the need for on-chip registers.
The high performing, easy-to-use ADS1602 is especially suitable for demanding measurement applications in sonar, vibration analysis, and data acquisition. The ADS1602 is offered in a small, 7mm × 7mm TQFP-48 package and is specified from –40°C to +85°C.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | 16-Bit, 2.5MSPS Analog-to-Digital Converter datasheet (Rev. E) | 2011/10/20 | |||
| 應用說明 | Digital Filter Types in Delta-Sigma ADCs (Rev. A) | PDF | HTML | 2023/3/29 | |||
| 應用說明 | ADS16xx Reference Options (Rev. A) | PDF | HTML | 2022/3/9 | |||
| 電子書 | Fundamentals of Precision ADC Noise Analysis (Rev. A) | 2020/6/19 | ||||
| 白皮書 | Voltage-reference impact on total harmonic distortion | 2016/8/1 | ||||
| 電子書 | Best of Baker's Best: Precision Data Converters -- Delta-Sigma ADCs | 2015/3/19 |
設計與開發
如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。
ANALOG-ENGINEER-CALC — PC software analog engineer's calculator
類比工程師的計算機旨在加速類比電路設計工程師定期使用的許多重複計算。此基於 PC 的工具提供圖形介面,列出各種常見計算,從使用回饋電阻器設定運算放大器增益到選擇適當的電路設計元件以穩定類比數位轉換器 (ADC) 驅動緩衝電路。
除了作為獨立工具使用外,此計算機還與類比工程師口袋參考中描述的概念相得益彰。
ADC-DAC-TO-VREF-SELECT-DESIGN-TOOL — The ADC-TO-VREF-SELECT tool enables the pairing of TI ADCs, DACs, and series voltage references.
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| TQFP (PFB) | 48 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。