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ADC3683-SP

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Radiation-hardened, QML-V, 300krad, 18 bit, two channel 65MSPS low-latency low-power ADC

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Data sheet

ADC3683-SP

ACTIVE
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Product details

Sample rate (max) (Msps) 65 Resolution (Bits) 18 Number of input channels 2 Interface type Serial LVDS Analog input BW (MHz) 200 Features Bypass Mode, Decimating Filter, Differential Inputs, Dual Channel, High Dynamic Range, High Performance, Internal Reference, LVDS interface, Low Power, Low latency Rating Space Peak-to-peak input voltage range (V) 3.2 Power consumption (typ) (mW) 186 Architecture SAR SNR (dB) 83 ENOB (Bits) 13.5 SFDR (dB) 85 Operating temperature range (°C) -55 to 105 Input buffer No Radiation, TID (typ) (krad) 300 Radiation, SEL (MeV·cm2/mg) 75
Sample rate (max) (Msps) 65 Resolution (Bits) 18 Number of input channels 2 Interface type Serial LVDS Analog input BW (MHz) 200 Features Bypass Mode, Decimating Filter, Differential Inputs, Dual Channel, High Dynamic Range, High Performance, Internal Reference, LVDS interface, Low Power, Low latency Rating Space Peak-to-peak input voltage range (V) 3.2 Power consumption (typ) (mW) 186 Architecture SAR SNR (dB) 83 ENOB (Bits) 13.5 SFDR (dB) 85 Operating temperature range (°C) -55 to 105 Input buffer No Radiation, TID (typ) (krad) 300 Radiation, SEL (MeV·cm2/mg) 75
CFP (HBP) 64 862.0096 mm² (29.36 mm × 29.36 mm)
  • Screening and radiation performance:
    • QMLV screening and reliability
    • Total ionizing dose (TID): 300krad (Si)
    • Single event latch-up (SEL): 75MeV-cm2/mg
  • Ambient temperature range: ­-55°C to 105°C
  • Dual channel ADC
  • 18-bit 65MSPS
  • Noise Floor: -160dBFS/Hz
  • Low power and optimized power scaling:
    • 64mW/ch (10MSPS)
    • 84mW/ch (65MSPS)
  • Latency:
    • 1 clock cycle in 1-wire mode
    • 2 clock cycles in 2-wire mode
  • 18-bit, no missing codes
  • INL: ±7LSB, DNL: ±0.7LSB
  • Internal or external reference
  • Input bandwidth: 200MHz (-3dB)
  • Optional digital down converter (DDC):
    • Real or complex decimation
    • Decimation by 2, 4, 8, 16, and 32
    • 32-bit NCO
  • Serial LVDS (SLVDS) interface (2-, 1-, and 1/2-wire)
  • Spectral performance (FIN = 5MHz):
    • SNR: 83.6dBFS
    • SFDR: 87.1dBc
    • Non HD23: 102dBC
  • Screening and radiation performance:
    • QMLV screening and reliability
    • Total ionizing dose (TID): 300krad (Si)
    • Single event latch-up (SEL): 75MeV-cm2/mg
  • Ambient temperature range: ­-55°C to 105°C
  • Dual channel ADC
  • 18-bit 65MSPS
  • Noise Floor: -160dBFS/Hz
  • Low power and optimized power scaling:
    • 64mW/ch (10MSPS)
    • 84mW/ch (65MSPS)
  • Latency:
    • 1 clock cycle in 1-wire mode
    • 2 clock cycles in 2-wire mode
  • 18-bit, no missing codes
  • INL: ±7LSB, DNL: ±0.7LSB
  • Internal or external reference
  • Input bandwidth: 200MHz (-3dB)
  • Optional digital down converter (DDC):
    • Real or complex decimation
    • Decimation by 2, 4, 8, 16, and 32
    • 32-bit NCO
  • Serial LVDS (SLVDS) interface (2-, 1-, and 1/2-wire)
  • Spectral performance (FIN = 5MHz):
    • SNR: 83.6dBFS
    • SFDR: 87.1dBc
    • Non HD23: 102dBC

The ADC3683-SP is a low latency, low noise, and ultra low power 18-bit 65MSPS high-speed dual channel ADC. Designed for best noise performance, the ADC delivers a noise spectral density of −160dBFS/Hz combined with excellent linearity and dynamic range. The ADC3683-SP offers DC precision together with IF sampling support to enable the design of a wide range of applications. The low latency architecture (as low as 1 clock cycle latency) and high sample rate also enable high speed control loops. The ADC consumes only 84mW/ch (1/2-swing enabled) at 65Msps and the power consumption scales well with sampling rate.

The device uses a serial LVDS (SLVDS) interface to output the data which minimizes the number of digital interconnects. The device also integrates a digital down converter (DDC) to help reduce the data rate and lower system power consumption. The ADC3683-SP is pin-to-pin compatible with the 14-bit, 125MSPS, ADC3664-SP. The device comes in a 64-pin CFP package (10.9mm x 10.9mm), and supports a temperature range from −55°C to +125°C.

The ADC3683-SP is a low latency, low noise, and ultra low power 18-bit 65MSPS high-speed dual channel ADC. Designed for best noise performance, the ADC delivers a noise spectral density of −160dBFS/Hz combined with excellent linearity and dynamic range. The ADC3683-SP offers DC precision together with IF sampling support to enable the design of a wide range of applications. The low latency architecture (as low as 1 clock cycle latency) and high sample rate also enable high speed control loops. The ADC consumes only 84mW/ch (1/2-swing enabled) at 65Msps and the power consumption scales well with sampling rate.

The device uses a serial LVDS (SLVDS) interface to output the data which minimizes the number of digital interconnects. The device also integrates a digital down converter (DDC) to help reduce the data rate and lower system power consumption. The ADC3683-SP is pin-to-pin compatible with the 14-bit, 125MSPS, ADC3664-SP. The device comes in a 64-pin CFP package (10.9mm x 10.9mm), and supports a temperature range from −55°C to +125°C.
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Technical documentation

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* Data sheet ADC3683-SP Radiation-Hardness-Assured 18-Bit, Dual Channel, 1 to 65MSPS, Low Latency, Low Noise, Ultra Low Power, Analog-to-Digital Converter (ADC) datasheet (Rev. A) PDF | HTML Dec 13, 2024
* Radiation & reliability report ADC3683-SP Total Ionizing Dose (TID) Radiation Report Feb 6, 2025
* Radiation & reliability report ADC3683-SP Single Event Effects Report (Rev. A) PDF | HTML Nov 22, 2024

Design & development

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Evaluation board

ADC3683EVMCVAL — ADC3683-SP evaluation module

The ADC3683 evaluation module (EVM) is designed to evaluate the ADC3683-SP high-speed analog-to-digital converter (ADC). The EVM is populated with the ADC3683-SP, an 18-bit, dual-channel 65MSPS ADC with serial LVDS interface.
User guide: PDF | HTML
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Simulation model

ADC3683-SP IBIS Model

SBAM518.ZIP (53 KB) - IBIS model
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Design tool

ADC-DAC-TO-VREF-SELECT-DESIGN-TOOL — The ADC-TO-VREF-SELECT tool enables the pairing of TI ADCs, DACs, and series voltage references.

The ADC-TO-VREF-SELECT tool enables the pairing of TI analog-to-digital converters (ADCs) and series voltage references. Users can select an ADC device and the desired reference voltage, and the tool will list up to two voltage reference recommendations.
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CFP (HBP) 64 Ultra Librarian
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