홈 마이크로컨트롤러(MCU) 및 프로세서 마이크로프로세서 및 DSP 멀티미디어 및 산업용 네트워킹 SoC
홈
마이크로컨트롤러(MCU) 및 프로세서
마이크로프로세서 및 DSP
멀티미디어 및 산업용 네트워킹 SoC

AM67

활성

HMI용 트리플 디스플레이, 3D 그래픽, PCIe 3, USB3, HMI용 4K 비디오 코덱을 지원하는 Arm® Cortex® -A53 SoC

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AM67

활성
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제품 상세 정보

CPU 4 Arm Cortex-A53 Frequency (MHz) 1400 Coprocessors 1 Arm Cortex-R5F Graphics acceleration 1 3D Display type 1 DSI, MIPI DPI, OLDI Protocols Ethernet, TSN PCIe 1 PCIe Gen 3 Hardware accelerators CPU only, Video decode accelerator, Video encode accelerator Features General purpose Operating system Android, Linux Security Secure boot TI functional safety category Functional Safety-Compliant Rating Catalog Power supply solution TPS65224 Operating temperature range (°C) -40 to 125 Edge AI enabled Yes
CPU 4 Arm Cortex-A53 Frequency (MHz) 1400 Coprocessors 1 Arm Cortex-R5F Graphics acceleration 1 3D Display type 1 DSI, MIPI DPI, OLDI Protocols Ethernet, TSN PCIe 1 PCIe Gen 3 Hardware accelerators CPU only, Video decode accelerator, Video encode accelerator Features General purpose Operating system Android, Linux Security Secure boot TI functional safety category Functional Safety-Compliant Rating Catalog Power supply solution TPS65224 Operating temperature range (°C) -40 to 125 Edge AI enabled Yes
FCBGA (AMW) 594 324 mm² 18 x 18

Processor Cores:

  • Up to Quad 64-bit Arm Cortex-A53 microprocessor subsystem at up to 1.4GHz
    • Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC
    • Each A53 core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection
  • Single-core Arm Cortex-R5F at up to 800MHz, integrated as part of MCU Channel with FFI
    • 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
    • 512KB SRAM with SECDED ECC
  • Single-core Arm Cortex-R5F at up to 800MHz, integrated to support Device Management
    • 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
  • Single-core Arm Cortex-R5F at up to 800MHz, integrated to support Run-time Management
    • 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
  • Two Deep Learning Accelerators (up to 4 TOPS total), each with:
    • C7x floating point, up to 40 GFLOPS, 256-bit Vector DSP at up to 1.0GHz
    • Matrix Multiply Accelerator (MMA), up to 2 TOPS (8b) at up to 1.0GHz
    • 32KB L1 DCache with SECDED ECC and 64KB L1 ICache with Parity protection
    • 2.25MB of L2 SRAM with SECDED ECC
  • Depth and Motion Processing Accelerators (DMPAC)
    • Dense Optical Flow (DOF) Accelerator
    • Stereo Disparity Engine (SDE) Accelerator
  • Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators:
    • 600MP/s ISP
    • Support for 12-bit RGB-IR
    • Support for up to 16-bit input RAW format
    • Line support up to 4096
    • Wide Dynamic Range (WDR), Lens Distortion Correction (LDC), Vision Imaging Subsystem (VISS), and Multi-Scalar (MSC) support
      • Output color format : 8-bits, 12-bits, and YUV 4:2:2, YUV 4:2:0, RGB, HSV/HSL

Multimedia:

  • Display subsystem
    • Triple display support over OLDI/LVDS (1x OLDI-DL, 1x or 2x OLDI-SL), DSI or DPI
      • OLDI-SL (Single Link): up to 1920 x 1080 at 60fps (165-MHz Pixel Clock)
      • OLDI-DL (Dual Link): up to 3840 x 1080 at 60fps (150-MHz Pixel Clock)
      • MIPI DSI: with 4 Lane MIPI® D-PHY supports up to 3840 x 1080 at 60fps (300-MHz Pixel Clock)
      • DPI (24-bit RGB parallel interface): up to 1920 x 1080 at 60fps (165-MHz pixel clock)
    • Four display pipelines with hardware overlay support. A maximum of two display pipelines may be used per display.
    • Supports safety features such as freeze frame detection and data correctness check
  • 3D Graphics Processing Unit
    • IMG BXS-4-64 with 256KB cache
    • Up to 50 GFLOPS
    • Single shader core
    • OpenGL ES3.2 and Vulkan 1.2 API support
  • Four Camera Serial Interface (CSI-2) Receiver with 4 Lane D-PHY
    • MIPI® CSI-2 v1.3 Compliant + MIPI® D-PHY 1.2
    • CSI-RX supports for 1,2,3, or 4 data lane mode up to 2.5Gbps per lane
  • One CSI2.0 Transmitter with 4 Lane D-PHY (shared with MIPI DSI)
    • CSI-TX supports for 1,2, or 4 data lane mode up to 2.5Gbps per lane
  • Video Encoder/Decoder
    • Support for HEVC (H.265) Main profiles at Level 5.1 High-tier
    • Support for H.264 BaseLine/Main/High Profiles at Level 5.2
    • Support for up to 4K UHD resolution (3840 × 2160)
      • Up to 400MP/s operation
  • Motion JPEG encode at 416MPixels/s withresolutions up to 4K UHD (3840 × 2160)

Memory Subsystem:

  • On-chip RAM dedicated to key processing cores
    • 256KB of On-Chip RAM (OCRAM) with SECDED ECC
    • 256KB of On-Chip RAM with SECDED ECC in SMS Subsystem
    • 512KB of On-chip RAM with SECDED ECC in Cortex-R5F MCU Subsystem
    • 64KB of On-chip RAM with SECDED ECC in R5F Device Manager Subsystem
    • 64KB of On-chip RAM with SECDED ECC in R5F Run-Time Manager Subsystem
    • 2.25MB of L2 SRAM with SECDED ECC in each C7x Deep Learning Accelerator (up to 4.5MB total)
  • DDR Subsystem (DDRSS)
    • Supports LPDDR4 memory types
    • 32-bit data bus with inline ECC
    • Supports speeds up to 4000MT/s
    • Max LPDDR4 size of 8GB

Functional Safety:

  • Functional Safety-Compliant targeted (on select part numbers)
    • Developed for functional safety applications
    • Documentation will be available to aid IEC 61508 functional safety system design
    • Systematic capability up to SIL 3 targeted
    • Hardware Integrity up to SIL 2 targeted
    • Safety-related certification
      • IEC 61508 planned

Security:

  • Secure boot supported
    • Hardware-enforced Root-of-Trust (RoT)
    • Support to switch RoT via backup key
    • Support for takeover protection, IP protection, and anti-roll back protection
  • Trusted Execution Environment (TEE) supported
    • Arm TrustZone based TEE
    • Extensive firewall support for isolation
    • Secure watchdog/timer/IPC
    • Secure storage support
    • Replay Protected Memory Block (RPMB) support
  • Dedicated Security Controller with user programmable HSM core and dedicated security DMA & IPC subsystem for isolated processing
  • Cryptographic acceleration supported
    • Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
  • Supports cryptographic cores
    • AES – 128-/192-/256-Bit key sizes
    • SHA2 – 224-/256-/384-/512-Bit key sizes
    • DRBG with true random number generator
    • PKA (Public Key Accelerator) to Assist in RSA/ECC processing for secure boot
  • Debugging security
    • Secure software controlled debug access
    • Security aware debugging

High-Speed Interfaces:

  • PCI-Express Gen3 single lane controller (PCIE)
    • Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
  • Integrated Ethernet switch supporting (total 2 external ports)
    • RMII(10/100) or RGMII (10/100/1000) or SGMII (1Gbps)
    • IEEE1588 (Annex D, Annex E, Annex F with 802.1AS PTP)
    • Clause 45 MDIO PHY management
    • Packet Classifier based on ALE engine with 512 classifiers
    • Priority based flow control
    • Time Sensitive Networking (TSN) support
    • Four CPU H/W interrupt Pacing
    • IP/UDP/TCP checksum offload in hardware
  • USB3.1-Gen1 Port
    • One enhanced SuperSpeed Gen1 port
    • Port configurable as USB host, USB peripheral, or USB Dual-Role Device
    • Integrated USB VBUS detection
  • USB2.0 Port
    • Port configurable as USB host, USB peripheral, or USB Dual-Role Device (DRD mode)
    • Integrated USB VBUS detection

General Connectivity and Automotive interfaces:

  • 9x Universal Asynchronous Receiver-Transmitters (UART)
  • 5x Serial Peripheral Interface (SPI) controllers
  • 7x Inter-Integrated Circuit (I2C) ports
  • 5x Multichannel Audio Serial Ports (McASP)
  • General-Purpose I/O (GPIO), All LVCMOS I/O can be configured as GPIO
  • 4x Controller Area Network (CAN) modules with CAN-FD support

Media and Data Storage:

  • 3x Secure Digital (SD) (4b+4b+8b) interfaces
    • 1x 8-bit eMMC interface up to HS400 speed
    • 2x 4-bit SD/SDIO interfaces up to UHS-I
    • Compliant with eMMC 5.1, SD 3.0, and SDIO Version 3.0
  • 1× General-Purpose Memory Controller (GPMC) up to 133MHz
  • OSPI/QSPI with DDR / SDR support
    • Support for Serial NAND and Serial NOR Flash
    • 4GBytes memory address support
    • XIP mode with optional on-the-fly encryption

Technology / Package:

  • 16-nm FinFET technology
  • 18 mm x 18 mm, 0.65 mm pitch with VCA (AMW)

Companion Power Management Solution:

  • Functional Safety-Compliant support up to ASIL-B or SIL-2 targeted
  • TPS6522x PMIC
  • TPS6287x Stackable, Fast Transient Bucks

Processor Cores:

  • Up to Quad 64-bit Arm Cortex-A53 microprocessor subsystem at up to 1.4GHz
    • Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC
    • Each A53 core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection
  • Single-core Arm Cortex-R5F at up to 800MHz, integrated as part of MCU Channel with FFI
    • 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
    • 512KB SRAM with SECDED ECC
  • Single-core Arm Cortex-R5F at up to 800MHz, integrated to support Device Management
    • 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
  • Single-core Arm Cortex-R5F at up to 800MHz, integrated to support Run-time Management
    • 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
  • Two Deep Learning Accelerators (up to 4 TOPS total), each with:
    • C7x floating point, up to 40 GFLOPS, 256-bit Vector DSP at up to 1.0GHz
    • Matrix Multiply Accelerator (MMA), up to 2 TOPS (8b) at up to 1.0GHz
    • 32KB L1 DCache with SECDED ECC and 64KB L1 ICache with Parity protection
    • 2.25MB of L2 SRAM with SECDED ECC
  • Depth and Motion Processing Accelerators (DMPAC)
    • Dense Optical Flow (DOF) Accelerator
    • Stereo Disparity Engine (SDE) Accelerator
  • Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators:
    • 600MP/s ISP
    • Support for 12-bit RGB-IR
    • Support for up to 16-bit input RAW format
    • Line support up to 4096
    • Wide Dynamic Range (WDR), Lens Distortion Correction (LDC), Vision Imaging Subsystem (VISS), and Multi-Scalar (MSC) support
      • Output color format : 8-bits, 12-bits, and YUV 4:2:2, YUV 4:2:0, RGB, HSV/HSL

Multimedia:

  • Display subsystem
    • Triple display support over OLDI/LVDS (1x OLDI-DL, 1x or 2x OLDI-SL), DSI or DPI
      • OLDI-SL (Single Link): up to 1920 x 1080 at 60fps (165-MHz Pixel Clock)
      • OLDI-DL (Dual Link): up to 3840 x 1080 at 60fps (150-MHz Pixel Clock)
      • MIPI DSI: with 4 Lane MIPI® D-PHY supports up to 3840 x 1080 at 60fps (300-MHz Pixel Clock)
      • DPI (24-bit RGB parallel interface): up to 1920 x 1080 at 60fps (165-MHz pixel clock)
    • Four display pipelines with hardware overlay support. A maximum of two display pipelines may be used per display.
    • Supports safety features such as freeze frame detection and data correctness check
  • 3D Graphics Processing Unit
    • IMG BXS-4-64 with 256KB cache
    • Up to 50 GFLOPS
    • Single shader core
    • OpenGL ES3.2 and Vulkan 1.2 API support
  • Four Camera Serial Interface (CSI-2) Receiver with 4 Lane D-PHY
    • MIPI® CSI-2 v1.3 Compliant + MIPI® D-PHY 1.2
    • CSI-RX supports for 1,2,3, or 4 data lane mode up to 2.5Gbps per lane
  • One CSI2.0 Transmitter with 4 Lane D-PHY (shared with MIPI DSI)
    • CSI-TX supports for 1,2, or 4 data lane mode up to 2.5Gbps per lane
  • Video Encoder/Decoder
    • Support for HEVC (H.265) Main profiles at Level 5.1 High-tier
    • Support for H.264 BaseLine/Main/High Profiles at Level 5.2
    • Support for up to 4K UHD resolution (3840 × 2160)
      • Up to 400MP/s operation
  • Motion JPEG encode at 416MPixels/s withresolutions up to 4K UHD (3840 × 2160)

Memory Subsystem:

  • On-chip RAM dedicated to key processing cores
    • 256KB of On-Chip RAM (OCRAM) with SECDED ECC
    • 256KB of On-Chip RAM with SECDED ECC in SMS Subsystem
    • 512KB of On-chip RAM with SECDED ECC in Cortex-R5F MCU Subsystem
    • 64KB of On-chip RAM with SECDED ECC in R5F Device Manager Subsystem
    • 64KB of On-chip RAM with SECDED ECC in R5F Run-Time Manager Subsystem
    • 2.25MB of L2 SRAM with SECDED ECC in each C7x Deep Learning Accelerator (up to 4.5MB total)
  • DDR Subsystem (DDRSS)
    • Supports LPDDR4 memory types
    • 32-bit data bus with inline ECC
    • Supports speeds up to 4000MT/s
    • Max LPDDR4 size of 8GB

Functional Safety:

  • Functional Safety-Compliant targeted (on select part numbers)
    • Developed for functional safety applications
    • Documentation will be available to aid IEC 61508 functional safety system design
    • Systematic capability up to SIL 3 targeted
    • Hardware Integrity up to SIL 2 targeted
    • Safety-related certification
      • IEC 61508 planned

Security:

  • Secure boot supported
    • Hardware-enforced Root-of-Trust (RoT)
    • Support to switch RoT via backup key
    • Support for takeover protection, IP protection, and anti-roll back protection
  • Trusted Execution Environment (TEE) supported
    • Arm TrustZone based TEE
    • Extensive firewall support for isolation
    • Secure watchdog/timer/IPC
    • Secure storage support
    • Replay Protected Memory Block (RPMB) support
  • Dedicated Security Controller with user programmable HSM core and dedicated security DMA & IPC subsystem for isolated processing
  • Cryptographic acceleration supported
    • Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
  • Supports cryptographic cores
    • AES – 128-/192-/256-Bit key sizes
    • SHA2 – 224-/256-/384-/512-Bit key sizes
    • DRBG with true random number generator
    • PKA (Public Key Accelerator) to Assist in RSA/ECC processing for secure boot
  • Debugging security
    • Secure software controlled debug access
    • Security aware debugging

High-Speed Interfaces:

  • PCI-Express Gen3 single lane controller (PCIE)
    • Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
  • Integrated Ethernet switch supporting (total 2 external ports)
    • RMII(10/100) or RGMII (10/100/1000) or SGMII (1Gbps)
    • IEEE1588 (Annex D, Annex E, Annex F with 802.1AS PTP)
    • Clause 45 MDIO PHY management
    • Packet Classifier based on ALE engine with 512 classifiers
    • Priority based flow control
    • Time Sensitive Networking (TSN) support
    • Four CPU H/W interrupt Pacing
    • IP/UDP/TCP checksum offload in hardware
  • USB3.1-Gen1 Port
    • One enhanced SuperSpeed Gen1 port
    • Port configurable as USB host, USB peripheral, or USB Dual-Role Device
    • Integrated USB VBUS detection
  • USB2.0 Port
    • Port configurable as USB host, USB peripheral, or USB Dual-Role Device (DRD mode)
    • Integrated USB VBUS detection

General Connectivity and Automotive interfaces:

  • 9x Universal Asynchronous Receiver-Transmitters (UART)
  • 5x Serial Peripheral Interface (SPI) controllers
  • 7x Inter-Integrated Circuit (I2C) ports
  • 5x Multichannel Audio Serial Ports (McASP)
  • General-Purpose I/O (GPIO), All LVCMOS I/O can be configured as GPIO
  • 4x Controller Area Network (CAN) modules with CAN-FD support

Media and Data Storage:

  • 3x Secure Digital (SD) (4b+4b+8b) interfaces
    • 1x 8-bit eMMC interface up to HS400 speed
    • 2x 4-bit SD/SDIO interfaces up to UHS-I
    • Compliant with eMMC 5.1, SD 3.0, and SDIO Version 3.0
  • 1× General-Purpose Memory Controller (GPMC) up to 133MHz
  • OSPI/QSPI with DDR / SDR support
    • Support for Serial NAND and Serial NOR Flash
    • 4GBytes memory address support
    • XIP mode with optional on-the-fly encryption

Technology / Package:

  • 16-nm FinFET technology
  • 18 mm x 18 mm, 0.65 mm pitch with VCA (AMW)

Companion Power Management Solution:

  • Functional Safety-Compliant support up to ASIL-B or SIL-2 targeted
  • TPS6522x PMIC
  • TPS6287x Stackable, Fast Transient Bucks

The AM67x scalable processor family is based on the evolutionary Jacinto™ 7 architecture, targeted at Smart Vision Camera and General Compute applications and built on extensive market knowledge accumulated over a decade of TI’s leadership in the Vision processor market. The AM67x family is built for a broad set of cost-sensitive high performance compute applications in Factory Automation, Building Automation, and other markets.

The AM67x provides high performance compute technology for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced vision camera applications. Key cores include the latest Arm and GPU processors for general compute, next generation DSP with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, an integrated next generation imaging subsystem (ISP), video codec, and MCU cores. All protected by industrial-grade security hardware accelerators.

AM67x contains up to four Arm® Cortex®-A53 cores with 64-bit architecture, a Vision Processing Accelerator (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators, Deep Learning (DL), Dense Optical Flow (DOF) video and 3D Graphics accelerators, a Cortex®-R5F MCU Island core and two Cortex®-R5F cores for Device and Run-time Management. The Cortex-A53s provide the powerful computing elements necessary for Linux applications as well as the implementation of traditional vision computing based algorithms. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite including RGB-InfraRed (RGB-IR), support for higher bit depth, and features targeting analytics applications. Key cores include two “C7x” next generation DSP with scalar and vector cores, dedicated “MMA” deep learning accelerator combined with a large 2.25MB L2 memory enabling performance up to 4 TOPS within the lowest power envelope in the industry when operating at the typical automotive worst case junction temperature of 125°C.

The AM67x integrates high-speed IOs including a PCIe Gen-3 (1L) and 3-port Gigabit Ethernet switch with one internal port and two external ports with TSN support. In addition, an extensive peripherals set is included in AM67x to enable system level connectivity such as USB, MMC/SD, four CSI2.0 Camera interface, OSPI, CAN-FD and GPMC for parallel host interface to an external ASIC/FPGA. AM67x supports secure boot for IP protection with the built-in HSM (Hardware Security Module) and employs advanced power management support for power-sensitive applications.

The AM67x scalable processor family is based on the evolutionary Jacinto™ 7 architecture, targeted at Smart Vision Camera and General Compute applications and built on extensive market knowledge accumulated over a decade of TI’s leadership in the Vision processor market. The AM67x family is built for a broad set of cost-sensitive high performance compute applications in Factory Automation, Building Automation, and other markets.

The AM67x provides high performance compute technology for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced vision camera applications. Key cores include the latest Arm and GPU processors for general compute, next generation DSP with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, an integrated next generation imaging subsystem (ISP), video codec, and MCU cores. All protected by industrial-grade security hardware accelerators.

AM67x contains up to four Arm® Cortex®-A53 cores with 64-bit architecture, a Vision Processing Accelerator (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators, Deep Learning (DL), Dense Optical Flow (DOF) video and 3D Graphics accelerators, a Cortex®-R5F MCU Island core and two Cortex®-R5F cores for Device and Run-time Management. The Cortex-A53s provide the powerful computing elements necessary for Linux applications as well as the implementation of traditional vision computing based algorithms. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite including RGB-InfraRed (RGB-IR), support for higher bit depth, and features targeting analytics applications. Key cores include two “C7x” next generation DSP with scalar and vector cores, dedicated “MMA” deep learning accelerator combined with a large 2.25MB L2 memory enabling performance up to 4 TOPS within the lowest power envelope in the industry when operating at the typical automotive worst case junction temperature of 125°C.

The AM67x integrates high-speed IOs including a PCIe Gen-3 (1L) and 3-port Gigabit Ethernet switch with one internal port and two external ports with TSN support. In addition, an extensive peripherals set is included in AM67x to enable system level connectivity such as USB, MMC/SD, four CSI2.0 Camera interface, OSPI, CAN-FD and GPMC for parallel host interface to an external ASIC/FPGA. AM67x supports secure boot for IP protection with the built-in HSM (Hardware Security Module) and employs advanced power management support for power-sensitive applications.

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기술 자료

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28개 모두 보기
상위 문서 유형 직함 형식 옵션 날짜
* Data sheet AM67x Processors datasheet (Rev. A) PDF | HTML 2024/09/30
* Errata J722S TDA4VEN TDA4AEN AM67 Processor Silicon Revision 1.0 Errata (Rev. A) PDF | HTML 2025/04/15
* User guide J722S TDA4VEN TDA4AEN AM67 Processor Silicon Revision 1.0 Technical Reference Manual (Rev. C) PDF | HTML 2025/11/25
Application note Thermal Management of TDA4x and AM6x PDF | HTML 2025/10/30
Application note Custom Board Design and Simulation Guidelines for Processor High Speed Parallel Interfaces (Rev. A) PDF | HTML 2025/09/05
Functional safety information TÜV SÜD Certificate for Functional Safety Software Development Process (Rev. D) 2025/06/17
Application note MCAN Debug Guide PDF | HTML 2025/02/18
Application note Microcontroller Abstraction Layer on Jacinto™ and Sitara™ Embedded Processors PDF | HTML 2025/01/28
User guide J722S/TDA4VEN/TDA4AEN/AM67 Power Estimation Tool User’s Guide (Rev. A) 2024/10/03
Application note Jacinto 7 LPDDR4 Board Design and Layout Guidelines (Rev. F) PDF | HTML 2024/08/05
Application note Debugging GPU Driver Issues on TDA4x and AM6x Devices PDF | HTML 2024/06/20
Application note Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design Guidelines (Rev. A) PDF | HTML 2024/06/04
Product overview J722S/AM67x/TDA4VEN/TDA4AEN Processor Automotive Power Designs using TPS6522312-Q1 PMIC PDF | HTML 2024/04/18
Application brief 스마트 다중 디스플레이 시스템을 위한 5가지 설계 고려 사항 PDF | HTML 2024/04/09
Application note Jacinto7 AM6x/TDA4x/DRA8x Schematic Checklist (Rev. B) PDF | HTML 2024/04/04
Application note Jacinto7 HS Device Customer Return Process PDF | HTML 2023/11/16
Application note Using TSN Ethernet Features to Improve Timing in Industrial Ethernet Controllers PDF | HTML 2023/11/15
White paper 고도로 통합된 프로세서를 사용해 효 율적인 에지 AI 시스템 설계 (Rev. A) PDF | HTML 2023/04/19
Application note UART Log Debug System on Jacinto 7 SoC PDF | HTML 2023/01/09
Product overview Jacinto™ 7 Safety Product Overview PDF | HTML 2022/08/15
Application note Dual-TDA4x System Solution PDF | HTML 2022/04/29
Application note SPI Enablement & Validation on TDA4 Family PDF | HTML 2022/04/05
Technical article How to simplify your embedded edge AI application development PDF | HTML 2022/01/28
Application note Enabling MAC2MAC Feature on Jacinto7 Soc 2022/01/10
Application note TDA4 Flashing Techniques PDF | HTML 2021/07/08
White paper Jacinto™ 7 프로세서의 보안 구현 도구 2021/01/04
White paper Jacinto™ 7 프로세서의 MCU 통합으로 차별화 지원 2020/10/22
Application note OSPI Tuning Procedure PDF | HTML 2020/07/08

설계 및 개발

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평가 보드

BEAGLEY-AI — AM67A 기반의 BeagleBoard.org Foundation BeagleY®-AI 단일 보드 컴퓨터

BeagleY® AI는 스마트 HMI(Human Machine Interface) 구축 프로세스를 간소화하고, 안정적인 임베디드 시스템에 카메라 및 고속 커넥티비티를 추가할 수 있도록 설계된 오픈 소스 단일 보드 컴퓨터입니다. 강력한 64비트, 쿼드 코어 A53 프로세서, C7x DSP와 페어링된 여러 개의 강력한 AI 가속기, 최대 3개의 동시 디스플레이 출력을 지원하는 통합 50 GFLOP GPU와 USB3.1, PCIe Gen 3, WiFi6 및 Bluetooth® 저에너지 5.4를 포함한 최신 연결 기능이 있습니다. 

이 (...)

발송: BeagleBoard.org Foundation
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평가 보드

EZURI-3P-CARBONAM67 — AM67 및 AM67A 프로세서용 Ezurio CarbonAM67 SOM, OSM-MF 시스템 온 모듈

Ezurio는 무선 모듈 및 시스템 온 모듈을 위한 최고의 제조업체이자 연결 전문가입니다. CarbonAM67 OSM-MF 제품군은 텍사스 인스트루먼트의 AM67x 프로세서 제품군, TI의 TPS65224 PMIC, Sona Wi-Fi 6 및 Bluetooth 무선 모듈에서 구동됩니다. 텍사스 인스트루먼트의 사내 USA 기반 어셈블리는 프로젝트 요구에 맞는 옵션을 제공합니다. 제품에 적용되는 RAM, eMMC 스토리지, Sona Wi-Fi 및 Bluetooth 연결, 캐리어 보드 사용자 지정을 선택합니다. 모든 CarbonAM67 (...)

발송: Ezurio
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디버그 프로브

TMDSEMU110-U — XDS110 JTAG 디버그 프로브

텍사스 인스트루먼트 XDS110은 TI 임베디드 프로세서를 위한 새로운 디버그 프로브(에뮬레이터)입니다. XDS110은 XDS100 제품군을 대체하면서 하나의 포드로 더 다양한 표준(IEEE1149.1, IEEE1149.7, SWD)을지원합니다. 또한 모든 XDS 디버그 프로브는 ETB(Embedded Trace Buffer)가 포함되어 있는 모든 Arm® 및 DSP 프로세서에서 코어(Core) 및 시스템 트레이스(System Trace)를 지원합니다.  핀을 통한 코어 추적의 경우 XDS560v2 PRO TRACE가 필요합니다.

(...)
사용 설명서: PDF
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TI.com에서 구매할 수 없음
디버그 프로브

TMDSEMU200-U — XDS200 USB 디버그 프로브

XDS200은 TI 임베디드 장치를 디버깅하는 데 사용되는 디버그 프로브(에뮬레이터)입니다. 대부분의 장치의 경우 더욱 저렴한 신형 XDS110(www.ti.com/tool/TMDSEMU110-U)을 사용하실 것을 권장합니다. XDS200은 단일 포드에서 다양한 표준(IEEE1149.1, IEEE1149.7, SWD)을 지원합니다. 모든 XDS 디버그 프로브는 ETB(임베디드 트레이스 버퍼)가 포함되어 있는 모든 Arm® 및 DSP 프로세서에서 코어 및 시스템 트레이스를 지원합니다.

XDS200은 TI 20핀 커넥터(TI 14핀, (...)

TI.com에서 구매할 수 없음
디버그 프로브

TMDSEMU560V2STM-UE — XDS560v2 시스템 추적 USB 및 이더넷 디버그 프로브

The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

TI.com에서 구매할 수 없음
디버그 프로브

LB-3P-TRACE32-ARM — Arm® 기반 마이크로컨트롤러 및 프로세서용 Lauterbach TRACE32® 디버그 및 트레이스 시스템

Lauterbach의 TRACE32® 툴은 개발자가 모든 종류의 Arm® 기반 마이크로컨트롤러 및 프로세서를 분석, 최적화 및 인증할 수 있도록 하는 첨단 하드웨어 및 소프트웨어 구성 요소 제품군입니다. 세계적으로 유명한 임베디드 시스템 및 SoC용 디버그 및 트레이스 솔루션은 초기 사전 실리콘 개발부터 현장의 제품 인증 및 문제 해결에 이르기까지 모든 개발 단계를 위한 완벽한 솔루션입니다. Lauterbach 툴의 직관적인 모듈형 설계는 엔지니어에게 현존하는 최고의 성능을 제공하고 요구 사항 변화에 따라 적응하고 성장하는 (...)

발송: Lauterbach GmbH
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소프트웨어 개발 키트(SDK)

PROCESSOR-SDK-ANDROID-AM67A — Processor SDK Android for AM67 and AM67A

The AM67A processor Linux® software development kits (SDKs) are unified software platforms for embedded processors providing easy setup and fast out-of-box access to benchmarks and demonstrations.

All releases of this SDK are consistent across TI's broad portfolio for which they are provided, (...)

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어
다운로드 옵션
소프트웨어 개발 키트(SDK)

PROCESSOR-SDK-LINUX-AM67 — Processor SDK Linux for AM67

The AM67 processor Linux® software development kits (SDKs) are unified software platforms for embedded processors providing easy setup and fast out-of-box access to benchmarks and demonstrations.

 

All releases of this SDK are consistent across TI's broad portfolio for which they are provided, (...)

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어
다운로드 옵션
코드 예제 또는 데모

KDAB-3P-QT-DEMOS — AM6 프로세서를 위한 Qt로 작성된 KDAB Group HMI(Human Machine Interface) 데모 소프트웨어 예제

텍사스 인스트루먼트 AM62 및 AM62P를 위한 KDAB 멀티 스크린 데모는 TI의 AM623, AM625, AM62P 프로세서의 확장 가능한 그래픽 및 디스플레이 기능을 보여줍니다. Qt로 제작된 이 데모는 멀티 디스플레이 렌더링, 부드러운 UI 성능, 하드웨어 가속 그래픽을 강조하여 다양한 애플리케이션에서 TI의 임베디드 프로세서의 유연성을 보여줍니다. AM62 제품군의 확장 가능한 성능은 비용에 민감한 산업용 HMI에서 고성능 에지 장치에 이르기까지 효율적인 배포를 가능하게 하여 원활한 사용자 환경을 보장합니다. 이 데모는 (...)
발송: KDAB Group
파트너 사이트 방문
시작하기

TI-DEVELOPER-ZONE — Start embedded development on your desktop or in the cloud

From evaluation to deployment the TI Developer Zone provides a comprehensive range of software, tools and training to ensure that you have everything you need for each stage of the development process.
지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어
시작하기
IDE, 구성, 컴파일러 또는 디버거

CCSTUDIO — Code Composer Studio integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It is comprised of a rich suite of tools used to build, debug, analyze and optimize embedded applications. Code Composer Studio is available across Windows®, Linux® and macOS® platforms.

(...)

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어
시작 다운로드 옵션
IDE, 구성, 컴파일러 또는 디버거

DDR-CONFIG-J722S — DDR Configuration Tool

This SysConfig based tool simplifies the process of configuring the DDR Subsystem Controller and PHY to interface to SDRAM devices. Based on the memory device, board design, and topology the tool outputs files to initialize and train the selected memory.
지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어
시작
IDE, 구성, 컴파일러 또는 디버거

SYSCONFIG — Standalone desktop version of SysConfig

SysConfig is a configuration tool designed to simplify hardware and software configuration challenges to accelerate software development.

SysConfig is available as part of the Code Composer Studio™ integrated development environment as well as a standalone application. Additionally SysConfig (...)

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어
시작 다운로드 옵션
운영 체제(OS)

TRZN-3P-TORIZON-OS — Torizon OS 즉시 사용 가능한 산업용 임베디드 Linux 배포판

Torizon OS는 높은 신뢰성과 보안을 요구하는 제품의 개발과 유지 관리를 단순화하는 데 중점을 둔 무료 오픈 소스 산업용 임베디드 Linux OS입니다. 이 OS는 핵심 서비스와 함께 최적화된 컨테이너 런타임과 안전한 오프라인 및 원격 OTA(오버 디 에어) 업데이트, 장치 모니터링, 원격 액세스를 위한 구성 요소를 제공합니다. Torizon OS는 간단한 커스터마이징만으로도 하드웨어에서 즉시 사용할 수 있으며, 기본적으로 보안이 적용되어 있고 자주 제공되는 업데이트와 쉽게 접근할 수 있는 간단한 보안 기능을 갖추고 (...)
발송: Torizon
파트너 사이트 방문
시뮬레이션 모델

J722S BSDL Model

SPRM854.ZIP (12 KB) - BSDL Model
다운로드
시뮬레이션 모델

J722S IBIS Model

SPRM855.ZIP (4140 KB) - IBIS Model
다운로드
시뮬레이션 모델

J722S Thermal Model

SPRM856.ZIP (0 KB) - Thermal Model
다운로드
거버(Gerber) 파일

J722S/AM67x/TDA4VEN/TDA4AEN Evaluation Module Design Files (Rev. C)

SPRR495C.ZIP (556217 KB)
다운로드
패키지 핀 CAD 기호, 풋프린트 및 3D 모델
FCBGA (AMW) 594 Ultra Librarian
TI의 평가 항목에 대한 표준 약관이 적용됩니다.

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.

지원 및 교육

TI 엔지니어의 기술 지원을 받을 수 있는 TI E2E™ 포럼

포럼 주제 모두 보기(영문)

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품질, 패키징, TI에서 주문하는 데 대한 질문이 있다면 TI 지원을 방문하세요. ​​​​​​​​​​​​​​

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