CDCLVD110A

ACTIVE

1-to-10 LVDS clock buffer up to 1100MHz with minimum skew for clock distribution

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Product details

Parameters

Function Differential Additive RMS jitter (Typ) (fs) 111 Output frequency (Max) (MHz) 1100 Number of outputs 10 VCC out (V) 2.5 VCC core (V) 2.5 Features 1:10 fanout, Individual output enable control Operating temperature range (C) -40 to 85 Rating Catalog Output type LVDS Input type LVDS open-in-new Find other Clock buffers

Package | Pins | Size

LQFP (VF) 32 49 mm² 7 x 7 VQFN (RHB) 32 25 mm² 5.0 x 5.0 open-in-new Find other Clock buffers

Features

  • Low-Output Skew <30 ps (Typical) for Clock-Distribution Applications
  • Distributes One Differential Clock Input to 10 LVDS Differential Clock Outputs
  • VCC Range: 2.5 V ±5%
  • Typical Signaling Rate Capability of Up to 1.1 GHz
  • Configurable Register (SI/CK) Individually Enables Disables Outputs, Selectable CLK0, CLK0 or CLK1, CLK1 Inputs
  • Full Rail-to-Rail Common-Mode Input Range
  • Receiver Input Threshold: ±100 mV
  • Available in 32-Pin LQFP and VQFN Package
  • Fail-Safe I/O-Pins for VDD = 0 V (Power Down)
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Description

The CDCLVD110A clock driver distributes one pair of differential LVDS clock inputs (either CLK0 or CLK1) to 10 pairs of differential clock outputs (Q0 to Q9) with minimum skew for clock distribution. The CDCLVD110A is specifically designed to drive 50-Ω transmission lines.

When the control enable is high (EN = 1), the 10 differential outputs are programmable in that each output can be individually enabled or disabled
(3-stated) according to the first 10 bits loaded into the shift register. Once the shift register is loaded, the last bit selects either CLK0 or CLK1 as the clock input. However, when EN = 0, the outputs are not programmable and all outputs are enabled.

The CDCLVD110A has an improved start-up circuit that minimizes enabling time in AC- and DC-coupled systems.

The CDCLVD110A is characterized for operation from –40°C to 85°C.

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Similar but not functionally equivalent to the compared device:
LMK00301 ACTIVE 3-GHz, 10-Output Differential Fanout Buffer / Level Translator Ultra low additive jitter, 10 output universal differential buffer

Technical documentation

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* Datasheet CDCLVD110A Programmable Low-Voltage 1:10 LVDS Clock Driver datasheet (Rev. D) Dec. 12, 2016

Design & development

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Design tools & simulation

SIMULATION MODELS Download
SCAC099.ZIP (13 KB) - IBIS Model

CAD/CAE symbols

Package Pins Download
LQFP (VF) 32 View options
VQFN (RHB) 32 View options

Ordering & quality

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