Ultra-Low Jitter Programmable Oscillator with Internal EEPROM
Product details
Parameters
Package | Pins | Size
Features
- Ultra-Low Noise, High Performance
- Jitter: 90-fs RMS Typical fOUT > 100 MHz on LMK61E07
- PSRR: –70 dBc, Robust Supply Noise Immunity on LMK61E07
- Flexible Output Format on LMK61E07
- LVPECL up to 1 GHz
- LVDS up to 900 MHz
- HCSL up to 400 MHz
- Total Frequency Tolerance of ±25 ppm
- System Level Features
- Glitch-Less Frequency Margining: Up to ±1000 ppm From Nominal
- Internal EEPROM: User Configurable Start-Up Settings
- Other Features
- Device Control: Fast Mode I2C up to 1000 kHz
- 3.3-V Operating Voltage
- Industrial Temperature Range (–40ºC to +85ºC)
- 7-mm × 5-mm 8-Pin Package
- Default Frequency:
- 70.656 MHz
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Description
The LMK61E07 family of ultra-low jitter PLLatinumTM programmable oscillators use fractional-N frequency synthesizers with integrated VCOs to generate commonly used reference clocks. The output on LMK61E07 can be configured as LVPECL, LVDS, or HCSL. The device features self start-up from on-chip EEPROM to generate a factory programmed default output frequency, or the device registers and EEPROM settings are fully programmable in-system through I2C serial interface. The device provides fine and coarse frequency margining control through I2C serial interface, making it a digitally-controlled oscillator (DCXO).
The PLL feedback divider can be updated to adjust the output frequency without spikes or glitches in steps of <1ppb using a PFD of 12.5 MHz (R divider=4, doubler disabled) for compatibility with xDSL requirements, or in steps of <5.2 ppb using a PFD of 100 MHz (R divider=1, doubler enabled) for compatibility with broadcast video requirements. The frequency margining features also facilitate system design verification tests (DVT), such as standards compliance and system timing margin testing.
Technical documentation
Type | Title | Date | |
---|---|---|---|
* | Datasheet | LMK61E07 Ultra-Low Jitter Programmable Oscillator With Internal EEPROM datasheet (Rev. A) | Oct. 08, 2018 |
Technical articles | How to select an optimal clocking solution for your FPGA-based design | Dec. 09, 2015 | |
User guide | LMK61FFEVM User's Guide (Rev. A) | Nov. 20, 2015 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
Description
The LMK61E2-156M25EVM evaluation module provides a complete platform to evaluate the 90-fs RMS jitter performance of Texas Instruments LMK61E2-156M25 Ultra-Low Jitter Fixed Frequency Oscillator.
The onboard power supply options allow for ease of use as well as configuration flexibility required (...)
Features
- Ultra low jitter differential clock generation
- Powered over USB or externally (SMA connector)
Design tools & simulation
Features
- Leverages Cadence PSpice Technology
- Preinstalled library with a suite of digital models to enable worst-case timing analysis
- Dynamic updates ensure you have access to most current device models
- Optimized for simulation speed without loss of accuracy
- Supports simultaneous analysis of multiple products
- (...)
CAD/CAE symbols
Package | Pins | Download |
---|---|---|
QFM (SIA) | 6 | View options |
Ordering & quality
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
Recommended products may have parameters, evaluation modules or reference designs related to this TI product.
Support & training
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