LMK61E07

• Ultra-Low Noise, High Performance
  • Jitter: 90-fs RMS Typical f_OUT > 100 MHz on LMK61E07
  • PSRR: –70 dBc, Robust Supply Noise Immunity on LMK61E07
• Flexible Output Format on LMK61E07
  • LVPECL up to 1 GHz
  • LVDS up to 900 MHz
  • HCSL up to 400 MHz
• Total Frequency Tolerance of ±25 ppm
• System Level Features
  • Glitch-Less Frequency Margining: Up to ±1000 ppm From Nominal
  • Internal EEPROM: User Configurable Start-Up Settings
• Other Features
  • Device Control: Fast Mode I²C up to 1000 kHz
  • 3.3-V Operating Voltage
  • Industrial Temperature Range (–40ºC to +85ºC)
  • 7-mm × 5-mm 8-Pin Package
• Default Frequency:
  • 70.656 MHz

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The LMK61E07 family of ultra-low jitter PLLatinum^TM programmable oscillators use fractional-N frequency synthesizers with integrated VCOs to generate commonly used reference clocks. The output on LMK61E07 can be configured as LVPECL, LVDS, or HCSL. The device features self start-up from on-chip EEPROM to generate a factory programmed default output frequency, or the device registers and EEPROM settings are fully programmable in-system through I²C serial interface. The device provides fine and coarse frequency margining control through I²C serial interface, making it a digitally-controlled oscillator (DCXO).

The PLL feedback divider can be updated to adjust the output frequency without spikes or glitches in steps of <1ppb using a PFD of 12.5 MHz (R divider=4, doubler disabled) for compatibility with xDSL requirements, or in steps of <5.2 ppb using a PFD of 100 MHz (R divider=1, doubler enabled) for compatibility with broadcast video requirements. The frequency margining features also facilitate system design verification tests (DVT), such as standards compliance and system timing margin testing.