Product details


Function Single-ended Additive RMS jitter (Typ) (fs) 19.2 Output frequency (Max) (MHz) 250 Number of outputs 2 Output supply voltage (V) 1.8, 2.5, 3.3 Core supply voltage (V) 1.8, 2.5, 3.3 Output skew (ps) 25 Features 1:2 fanout, Synchronous output enable Operating temperature range (C) -40 to 125 Rating Catalog Output type LVCMOS Input type LVCMOS open-in-new Find other Clock buffers

Package | Pins | Size

TSSOP (PW) 8 19 mm² 3 x 6.4 open-in-new Find other Clock buffers


  • High-performance 1:4 LVCMOS clock buffer
  • Very low output skew < 50 ps
  • Extremely low additive jitter < 50-fs maximum
    • 7.5-fs typical at VDD = 3.3 V
    • 10-fs typical at VDD = 2.5 V
    • 19.2-fs typical at VDD = 1.8 V
  • Very low propagation delay < 3 ns
  • Synchronous output enable
  • Supply voltage: 3.3-V, 2.5-V, or 1.8-V
    • 3.3-V tolerant input at all supply voltages
  • fmax = 250 MHz for 3.3 V
    fmax = 200-MHz for 2.5 V and 1.8 V
  • Operating temperature range: –40°C to 125°C
  • Available in 8-pin TSSOP package

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The LMK1C110x is a modular, high-performance, low-skew, general-purpose clock buffer family from Texas Instruments.

The entire family is designed with a modular approach in mind. Three different fan-out variations, 1:2, 1:3, 1:4, are available.

All of the devices within this family are pin-compatible to each other and backwards compatible to the CDCLVC110x family for easy handling.

All family members share the same high performing characteristics such as low additive jitter, low skew, and wide operating temperature range.

The LMK1C110x supports a synchronous output enable control (1G) which switches the outputs into a low state when 1G is low.

The LMK1C110x family operates in a 1.8-V, 2.5-V and 3.3-V environment and are characterized for operation from –40°C to 125°C.

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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet LMK1C110x 1.8-V, 2.5-V, and 3.3-V LVCMOS Clock Buffer Family datasheet (Rev. B) Jun. 16, 2020
Application notes LMK1C110x Key Performance in System Level (Rev. A) Mar. 10, 2020

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

document-generic User guide
LMK1C1104 is a high-performance, low additive jitter LVCMOS clock buffer with one LVCMOS input, four LVCMOS outputs, and a global output enable pin. This evaluation module (EVM) is designed to demonstrate the electrical performance of the LMK1C1104, however, this EVM can also be used to evaluate (...)
  • Easy to use evaluation board to fan-out up to 4 LVCMOS clocks with low phase noise/jitter
  • Output enable pin configurable through jumper
  • Board powered from a single 3.3V / 2.5V / 1.8V / 1.5V supply
  • Board supports up to eight clock outputs for pin compatible TSSOP devices in the industry standard (...)

Design tools & simulation

PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
SNAR039.ZIP (498 KB)

CAD/CAE symbols

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TSSOP (PW) 8 View options

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