Home Clocks & timing Clock buffers
Home
Clocks & timing
Clock buffers

LMK00334-Q1

ACTIVE

Automotive 4-output PCIe® Gen1/Gen2/Gen3/Gen4/Gen5 clock buffer and level translator

Order now
Data sheet

LMK00334-Q1

ACTIVE
Order now

Product details

Number of outputs 4 Additive RMS jitter (typ) (fs) 30 Core supply voltage (V) 3.3 Output supply voltage (V) 2.5, 3.3 Output skew (ps) 50 Operating temperature range (°C) -40 to 105 Rating Automotive Output type HCSL, LVCMOS Input type CML, HCSL, HSTL, LVCMOS, LVDS, LVPECL, SSTL, XTAL
Number of outputs 4 Additive RMS jitter (typ) (fs) 30 Core supply voltage (V) 3.3 Output supply voltage (V) 2.5, 3.3 Output skew (ps) 50 Operating temperature range (°C) -40 to 105 Rating Automotive Output type HCSL, LVCMOS Input type CML, HCSL, HSTL, LVCMOS, LVDS, LVPECL, SSTL, XTAL
WQFN (RTV) 32 25 mm² (5 mm × 5 mm)
  • AEC-Q100 Qualified for Automotive Applications:
    • Device Temperature Grade 2: –40°C to 105°C Ambient Operating Temperature Range
    • Device HBM ESD Classification Level 2
    • Device CDM ESD Classification Level C5
    • Device MM ESD Classification Level M2
  • 3:1 Input multiplexer
    • Two universal inputs operate up to 400 MHz and accept LVPECL, LVDS, CML, SSTL, HSTL, HCSL, or single-ended clocks
    • One crystal input accepts a 10- to 40-MHz crystal or single-ended clock
  • Two banks with two differential outputs each
    • HCSL, or Hi-Z (selectable)
    • Additive RMS phase jitter for PCIe Gen3/Gen4 at 100 MHz:
      • 30 fs RMS (typical)
  • High PSRR: –72 dBc at 156.25 MHz
  • LVCMOS output with synchronous enable input
  • Pin-controlled configuration
  • VCC core supply: 3.3 V ± 5%
  • Three independent VCCO output supplies: 3.3 V, 2.5 V ± 5%
  • Industrial temperature range: –40°C to +105°C
  • 32-pin WQFN (5 mm × 5 mm)
  • AEC-Q100 Qualified for Automotive Applications:
    • Device Temperature Grade 2: –40°C to 105°C Ambient Operating Temperature Range
    • Device HBM ESD Classification Level 2
    • Device CDM ESD Classification Level C5
    • Device MM ESD Classification Level M2
  • 3:1 Input multiplexer
    • Two universal inputs operate up to 400 MHz and accept LVPECL, LVDS, CML, SSTL, HSTL, HCSL, or single-ended clocks
    • One crystal input accepts a 10- to 40-MHz crystal or single-ended clock
  • Two banks with two differential outputs each
    • HCSL, or Hi-Z (selectable)
    • Additive RMS phase jitter for PCIe Gen3/Gen4 at 100 MHz:
      • 30 fs RMS (typical)
  • High PSRR: –72 dBc at 156.25 MHz
  • LVCMOS output with synchronous enable input
  • Pin-controlled configuration
  • VCC core supply: 3.3 V ± 5%
  • Three independent VCCO output supplies: 3.3 V, 2.5 V ± 5%
  • Industrial temperature range: –40°C to +105°C
  • 32-pin WQFN (5 mm × 5 mm)

The LMK00334 -Q1 device is a 4-output HCSL fanout buffer intended for high-frequency, low-jitter clock, data distribution, and level translation. It is capable of distributing the reference clock for ADCs, DACs, multi-gigabit ethernet, XAUI, fibre channel, SATA/SAS, SONET/SDH, CPRI, and high-frequency backplanes.

The input clock can be selected from two universal inputs or one crystal input. The selected input clock is distributed to two banks of two HCSL outputs and one LVCMOS output. The LVCMOS output has a synchronous enable input for runt-pulse-free operation when enabled or disabled. The LMK00334 -Q1 operates from a 3.3-V core supply and three independent 3.3-V or 2.5-V output supplies.

The LMK00334 -Q1 provides high performance, versatility, and power efficiency, making it ideal for replacing fixed-output buffer devices while increasing timing margin in the system.

The LMK00334 -Q1 device is a 4-output HCSL fanout buffer intended for high-frequency, low-jitter clock, data distribution, and level translation. It is capable of distributing the reference clock for ADCs, DACs, multi-gigabit ethernet, XAUI, fibre channel, SATA/SAS, SONET/SDH, CPRI, and high-frequency backplanes.

The input clock can be selected from two universal inputs or one crystal input. The selected input clock is distributed to two banks of two HCSL outputs and one LVCMOS output. The LVCMOS output has a synchronous enable input for runt-pulse-free operation when enabled or disabled. The LMK00334 -Q1 operates from a 3.3-V core supply and three independent 3.3-V or 2.5-V output supplies.

The LMK00334 -Q1 provides high performance, versatility, and power efficiency, making it ideal for replacing fixed-output buffer devices while increasing timing margin in the system.
filter Find other Clock buffers
Download View video with transcript Video

Similar products you might be interested in

open-in-new Compare alternates
Same functionality with different pin-out to the compared device.
CDCDB800 ACTIVE 8-output clock buffer for PCIe® Gen 1 to Gen 7 DB800ZL compliant with output enable/disable

Technical documentation

No results found. Please clear your search and try again.
View all 2
Top documentation Type Title Format options Date
* Data sheet LMK00334-Q1 Four-Output Clock Buffer and Level Translator for PCIe Gen 1 to Gen 5 datasheet (Rev. A) PDF | HTML Jan 19, 2022
Application note Clocking for PCIe Applications PDF | HTML Nov 28, 2023

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

LMK00338EVM — LMK00338 PCIe Gen1/2/3 Clock Buffer Evaluation Module

The LMK00338 is a 400MHz, 8-output HCSL buffer intended for PCIe Gen1/2/3 Applications, low additive jitter clock distribution and level translation. The EVM allows the user to verify the functionality and performance specification of the device. Refer to the LMK00338 datasheet for the functional (...)

User guide: PDF
Supported products & hardware
In stock
Limit:
??asset.out-of-stock-ti_en_US??
Not available
Simulation model

LMK00334 IBIS Model

SNAM160A (100 KB) - IBIS model
Supported products & hardware
Design tool

CLOCK-TREE-ARCHITECT — Clock tree architect programming software

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.

Supported products & hardware
Design tool

PLLATINUMSIM-SW — PLL loop filter, phase noise, lock time, and spur simulation tool

PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.

Supported products & hardware
Package Pins CAD symbols, footprints & 3D models
WQFN (RTV) 32 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

Ordering & quality

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

TI E2E™ forums with technical support from TI engineers

View all forum topics

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos