Product details

Function Differential, Fanout, Level translator Additive RMS jitter (typ) (fs) 30 Output frequency (max) (MHz) 400 Number of outputs 4 Output supply voltage (V) 2.5, 3.3 Core supply voltage (V) 3.3 Output skew (ps) 50 Features PCIe Gen 5 Compliant Operating temperature range (°C) -40 to 105 Rating Automotive Output type HCSL, LVCMOS Input type CML, HCSL, HSTL, LVCMOS, LVDS, LVPECL, SSTL, XTAL
Function Differential, Fanout, Level translator Additive RMS jitter (typ) (fs) 30 Output frequency (max) (MHz) 400 Number of outputs 4 Output supply voltage (V) 2.5, 3.3 Core supply voltage (V) 3.3 Output skew (ps) 50 Features PCIe Gen 5 Compliant Operating temperature range (°C) -40 to 105 Rating Automotive Output type HCSL, LVCMOS Input type CML, HCSL, HSTL, LVCMOS, LVDS, LVPECL, SSTL, XTAL
WQFN (RTV) 32 25 mm² 5 x 5
  • AEC-Q100 Qualified for Automotive Applications:
    • Device Temperature Grade 2: –40°C to 105°C Ambient Operating Temperature Range
    • Device HBM ESD Classification Level 2
    • Device CDM ESD Classification Level C5
    • Device MM ESD Classification Level M2
  • 3:1 Input multiplexer
    • Two universal inputs operate up to 400 MHz and accept LVPECL, LVDS, CML, SSTL, HSTL, HCSL, or single-ended clocks
    • One crystal input accepts a 10- to 40-MHz crystal or single-ended clock
  • Two banks with two differential outputs each
    • HCSL, or Hi-Z (selectable)
    • Additive RMS phase jitter for PCIe Gen3/Gen4 at 100 MHz:
      • 30 fs RMS (typical)
  • High PSRR: –72 dBc at 156.25 MHz
  • LVCMOS output with synchronous enable input
  • Pin-controlled configuration
  • VCC core supply: 3.3 V ± 5%
  • Three independent VCCO output supplies: 3.3 V, 2.5 V ± 5%
  • Industrial temperature range: –40°C to +105°C
  • 32-pin WQFN (5 mm × 5 mm)
  • AEC-Q100 Qualified for Automotive Applications:
    • Device Temperature Grade 2: –40°C to 105°C Ambient Operating Temperature Range
    • Device HBM ESD Classification Level 2
    • Device CDM ESD Classification Level C5
    • Device MM ESD Classification Level M2
  • 3:1 Input multiplexer
    • Two universal inputs operate up to 400 MHz and accept LVPECL, LVDS, CML, SSTL, HSTL, HCSL, or single-ended clocks
    • One crystal input accepts a 10- to 40-MHz crystal or single-ended clock
  • Two banks with two differential outputs each
    • HCSL, or Hi-Z (selectable)
    • Additive RMS phase jitter for PCIe Gen3/Gen4 at 100 MHz:
      • 30 fs RMS (typical)
  • High PSRR: –72 dBc at 156.25 MHz
  • LVCMOS output with synchronous enable input
  • Pin-controlled configuration
  • VCC core supply: 3.3 V ± 5%
  • Three independent VCCO output supplies: 3.3 V, 2.5 V ± 5%
  • Industrial temperature range: –40°C to +105°C
  • 32-pin WQFN (5 mm × 5 mm)

The LMK00334 -Q1 device is a 4-output HCSL fanout buffer intended for high-frequency, low-jitter clock, data distribution, and level translation. It is capable of distributing the reference clock for ADCs, DACs, multi-gigabit ethernet, XAUI, fibre channel, SATA/SAS, SONET/SDH, CPRI, and high-frequency backplanes.

The input clock can be selected from two universal inputs or one crystal input. The selected input clock is distributed to two banks of two HCSL outputs and one LVCMOS output. The LVCMOS output has a synchronous enable input for runt-pulse-free operation when enabled or disabled. The LMK00334 -Q1 operates from a 3.3-V core supply and three independent 3.3-V or 2.5-V output supplies.

The LMK00334 -Q1 provides high performance, versatility, and power efficiency, making it ideal for replacing fixed-output buffer devices while increasing timing margin in the system.

The LMK00334 -Q1 device is a 4-output HCSL fanout buffer intended for high-frequency, low-jitter clock, data distribution, and level translation. It is capable of distributing the reference clock for ADCs, DACs, multi-gigabit ethernet, XAUI, fibre channel, SATA/SAS, SONET/SDH, CPRI, and high-frequency backplanes.

The input clock can be selected from two universal inputs or one crystal input. The selected input clock is distributed to two banks of two HCSL outputs and one LVCMOS output. The LVCMOS output has a synchronous enable input for runt-pulse-free operation when enabled or disabled. The LMK00334 -Q1 operates from a 3.3-V core supply and three independent 3.3-V or 2.5-V output supplies.

The LMK00334 -Q1 provides high performance, versatility, and power efficiency, making it ideal for replacing fixed-output buffer devices while increasing timing margin in the system.

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Technical documentation

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* Data sheet LMK00334-Q1 Four-Output Clock Buffer and Level Translator for PCIe Gen 1 to Gen 5 datasheet (Rev. A) PDF | HTML 19 Jan 2022
EVM User's guide LMK00338EVM User's Guide 13 Dec 2013

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

LMK00338EVM — LMK00338 PCIe Gen1/2/3 Clock Buffer Evaluation Module

The LMK00338 is a 400MHz, 8-output HCSL buffer intended for PCIe Gen1/2/3 Applications, low additive jitter clock distribution and level translation. The EVM allows the user to verify the functionality and performance specification of the device. Refer to the LMK00338 datasheet for the functional (...)

User guide: PDF
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Simulation model

LMK00334 IBIS Model

SNAM160.ZIP (100 KB) - IBIS Model
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CLOCK-TREE-ARCHITECT — Clock tree architect programming software

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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