LMK00338

ACTIVE

8-output PCIe Gen1/2/3 clock buffer/level translator

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Product details

Parameters

Function Differential, Fanout Additive RMS jitter (Typ) (fs) 30 Output frequency (Max) (MHz) 400 Number of outputs 8 Output supply voltage (V) 2.5, 3.3 Core supply voltage (V) 3.3 Output skew (ps) 50 Features PCIe 3.0 Compliant Operating temperature range (C) -40 to 85 Rating Catalog Output type HCSL, LVCMOS Input type CML, HCSL, HSTL, LVCMOS, LVDS, LVPECL, LVTTL, SSTL, XTAL open-in-new Find other Clock buffers

Package | Pins | Size

WQFN (RTA) 40 36 mm² 6 x 6 open-in-new Find other Clock buffers

Features

  • 3:1 Input Multiplexer
    • Two Universal Inputs Operate up to 400 MHz and Accept LVPECL, LVDS, CML, SSTL, HSTL, HCSL, or Single-Ended Clocks
    • One Crystal Input Accepts a 10-MHz to 40-MHz Crystal or Single-Ended Clock
  • Two Banks With 4 Differential Outputs Each
    • HCSL, or Hi-Z (Selectable per Bank)
    • Additive RMS Phase Jitter for PCIe Gen3 at 100 MHz:
      • 30 fs RMS (Typical)
  • –72 dBc at 156.25 MHz
  • LVCMOS Output With Synchronous Enable Input
  • Pin-Controlled Configuration
  • VCC Core Supply: 3.3 V ± 5%
  • 3 Independent VCCO Output Supplies: 3.3 V/2.5 V ± 5%
  • Industrial Temperature Range: –40°C to +85°C
  • 40-lead WQFN (6 mm × 6 mm)

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Description

The LMK00338 device is an 8-output PCIe Gen1/Gen2/Gen3 fanout buffer intended for high-frequency, low-jitter clock, data distribution, and level translation. The input clock can be selected from two universal inputs or one crystal input. The selected input clock is distributed to two banks of 4 HCSL outputs and one LVCMOS output. The LVCMOS output has a synchronous enable input for runt-pulse-free operation when enabled or disabled. The LMK00338 operates from a 3.3-V core supply and 3 independent 3.3-V or 2.5-V output supplies.

The LMK00338 provides high performance, versatility, and power efficiency, making it ideal for replacing fixed-output buffer devices while increasing timing margin in the system.

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LMK00308 ACTIVE 3.1-GHz differential clock buffer/level translator with 8 configurable outputs Low additive jitter ,1:8 Universal differential buffer that can support HCSL

Technical documentation

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Type Title Date
* Data sheet LMK00338 8-Output Differential Clock Buffer and Level Translator datasheet (Rev. B) Jun. 02, 2017
Technical article Timing is Everything: How to optimize clock distribution in PCIe applications Mar. 28, 2014
User guide LMK00338EVM User's Guide Dec. 13, 2013

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
document-generic User guide
299
Description

The LMK00338 is a 400MHz, 8-output HCSL buffer intended for PCIe Gen1/2/3 Applications, low additive jitter clock distribution and level translation. The EVM allows the user to verify the functionality and performance specification of the device. Refer to the LMK00338 datasheet for the functional (...)

Features
  • Low-noise clock fan-out with two banks of four HCSL outputs each and one LVCMOS output
  • 3:1 input multiplexer with two universal input buffers and one crystal oscillator interface, selectable via control pins
  • Includes DIP switches to configure control pins
  • 3.3 V core and independent 3.3 V/2.5 V output (...)

Design tools & simulation

SIMULATION MODEL Download
SNAM161.ZIP (107 KB) - IBIS Model
SIMULATION TOOL Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
DESIGN TOOL Download
Clock tree architect programming software
CLOCK-TREE-ARCHITECT Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
Features
  • Accepts customer specific design requirements such as input frequencies, output frequencies, clock formats and clock counts
  • Generates clock trees by taking into account a variety of advanced specifications, such as noise floor and phase determinism requirements
  • Presents clear and intuitive block (...)

CAD/CAE symbols

Package Pins Download
WQFN (RTA) 40 View options

Ordering & quality

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