Ultra-Low Jitter Standard Differential Oscillator - 125M00
Product details
Parameters
Package | Pins | Size
Features
- Ultra-low Noise, High Performance
- Jitter: 90 fs RMS Typical Fout > 100 MHz
- PSRR: –70 dBc, Robust Supply Noise Immunity
- Supported Output Format
- LVPECL up to 1 GHz
- LVDS up to 900 MHz
- HCSL up to 400 MHz
- Total Frequency Tolerance of ± 50 ppm (LMK61X2) and ± 25 ppm (LMK61X0)
- 3.3-V Operating Voltage
- Industrial Temperature Range (–40ºC to +85ºC)
- 7 mm × 5 mm 6-Pin Package, Pin-Compatible With Industry Standard 7050 XO Package
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Description
The LMK61XX is an ultra-low jitter oscillator that generates a commonly used reference clock. The device is pre-programmed in factory to support any reference clock frequency; supported output formats are LVPECL up to 1 GHz, LVDS up to 900 MHz, and HCSL up to 400 MHz. Internal power conditioning provide excellent power supply ripple rejection (PSRR), reducing the cost and complexity of the power delivery network. The device operates from a single 3.3 V ± 5% supply.
Technical documentation
| Type | Title | Date | |
|---|---|---|---|
| * | Datasheet | LMK61XX High-Performance Ultra-Low Jitter Oscillator datasheet (Rev. D) | Oct. 19, 2017 |
| Technical articles | How to select an optimal clocking solution for your FPGA-based design | Dec. 09, 2015 | |
| User guides | LMK61FFEVM User's Guide (Rev. A) | Nov. 20, 2015 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
Description
The LMK61E2-125M00EVM evaluation module provides a complete platform to evaluate the 90-fs RMS jitter performance of Texas Instruments LMK61E2-125M00 Ultra-Low Jitter Fixed Frequency Oscillator.
The onboard power supply options allow for ease of use as well as configuration flexibility required in (...)
Features
- Ultra low jitter differential clock generation
- Powered over USB or externally (SMA connector)
Design tools & simulation
Features
- Leverages Cadence PSpice Technology
- Preinstalled library with a suite of digital models to enable worst-case timing analysis
- Dynamic updates ensure you have access to most current device models
- Optimized for simulation speed without loss of accuracy
- Supports simultaneous analysis of multiple products
- (...)
CAD/CAE symbols
| Package | Pins | Download |
|---|---|---|
| QFM (SIA) | 6 | View options |
Ordering & quality
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Support & training
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