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CDCLVD1208

ACTIVE

Low jitter, 2-input selectable 1:8 universal-to-LVDS buffer

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Data sheet

CDCLVD1208

ACTIVE
Data sheet Order now

Product details

Number of outputs 8 Additive RMS jitter (typ) (fs) 171 Core supply voltage (V) 2.5 Output supply voltage (V) 2.5 Output skew (ps) 45 Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVDS Input type LVCMOS, LVDS, LVPECL
Number of outputs 8 Additive RMS jitter (typ) (fs) 171 Core supply voltage (V) 2.5 Output supply voltage (V) 2.5 Output skew (ps) 45 Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVDS Input type LVCMOS, LVDS, LVPECL
VQFN (RHD) 28 25 mm² (5 mm × 5 mm)
  • 2:8 Differential Buffer
  • Low Additive Jitter: < 300-fs RMS in 10-kHz to 20-MHz
  • Low Output Skew of 45 ps (Maximum)
  • Universal Inputs Accept LVDS, LVPECL, and LVCMOS
  • Selectable Clock Inputs Through Control Pin
  • 8 LVDS Outputs, ANSI EIA/TIA-644A Standard Compatible
  • Clock Frequency: Up to 800 MHz
  • Device Power Supply: 2.375 V to 2.625 V
  • LVDS Reference Voltage, VAC_REF, Available for Capacitive Coupled Inputs
  • Industrial Temperature Range: –40°C to 85°C
  • Packaged in 5-mm × 5-mm, 28-Pin VQFN (RHD)
  • ESD Protection Exceeds 3-kV HBM, 1-kV CDM
  • APPLICATIONS
    • Telecommunications and Networking
    • Medical Imaging
    • Test and Measurement Equipment
    • Wireless Communications
    • General-Purpose Clocking

All other trademarks are the property of their respective owners
  • 2:8 Differential Buffer
  • Low Additive Jitter: < 300-fs RMS in 10-kHz to 20-MHz
  • Low Output Skew of 45 ps (Maximum)
  • Universal Inputs Accept LVDS, LVPECL, and LVCMOS
  • Selectable Clock Inputs Through Control Pin
  • 8 LVDS Outputs, ANSI EIA/TIA-644A Standard Compatible
  • Clock Frequency: Up to 800 MHz
  • Device Power Supply: 2.375 V to 2.625 V
  • LVDS Reference Voltage, VAC_REF, Available for Capacitive Coupled Inputs
  • Industrial Temperature Range: –40°C to 85°C
  • Packaged in 5-mm × 5-mm, 28-Pin VQFN (RHD)
  • ESD Protection Exceeds 3-kV HBM, 1-kV CDM
  • APPLICATIONS
    • Telecommunications and Networking
    • Medical Imaging
    • Test and Measurement Equipment
    • Wireless Communications
    • General-Purpose Clocking

All other trademarks are the property of their respective owners

The CDCLVD1208 clock buffer distributes one of two selectable clock inputs (IN0 and IN1) to 8 pairs of differential LVDS clock outputs (OUT0 through OUT7) with minimum skew for clock distribution. The CDCLVD1208 can accept two clock sources into an input multiplexer. The inputs can either be LVDS, LVPECL, or LVCMOS.

The CDCLVD1208 is specifically designed for driving 50-Ω transmission lines. In case of driving the inputs in single-ended mode, the appropriate bias voltage, VAC_REF, must be applied to the unused negative input pin.

The IN_SEL pin selects the input which is routed to the outputs. If this pin is left open, it disables the outputs (static). The part supports a fail-safe function. The device incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

The device operates in 2.5-V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD1208 is packaged in small, 28-pin, 5-mm × 5-mm VQFN package.

The CDCLVD1208 clock buffer distributes one of two selectable clock inputs (IN0 and IN1) to 8 pairs of differential LVDS clock outputs (OUT0 through OUT7) with minimum skew for clock distribution. The CDCLVD1208 can accept two clock sources into an input multiplexer. The inputs can either be LVDS, LVPECL, or LVCMOS.

The CDCLVD1208 is specifically designed for driving 50-Ω transmission lines. In case of driving the inputs in single-ended mode, the appropriate bias voltage, VAC_REF, must be applied to the unused negative input pin.

The IN_SEL pin selects the input which is routed to the outputs. If this pin is left open, it disables the outputs (static). The part supports a fail-safe function. The device incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

The device operates in 2.5-V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD1208 is packaged in small, 28-pin, 5-mm × 5-mm VQFN package.
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* Data sheet CDCLVD1208 2:8 Low Additive Jitter LVDS Buffer datasheet (Rev. A) PDF | HTML Oct 31, 2016

Design & development

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Evaluation board

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CDCLVD1208 IBIS Model (Rev. B)

SLLM090B.ZIP (14 KB) - IBIS model
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VQFN (RHD) 28 Ultra Librarian
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