Low jitter, 1:8 LVCMOS fan-out clock buffer
Product details
Parameters
Package | Pins | Size
Features
- High-Performance 1:2, 1:3, 1:4, 1:6, 1:8, 1:10, 1:12 LVCMOS Clock Buffer Family
- Very Low Pin-to-Pin Skew < 50 ps
- Very Low Additive Jitter < 100 fs
- Supply Voltage: 3.3 V or 2.5 V
- fmax = 250 MHz for 3.3 V
fmax = 180 MHz for 2.5 V - Operating Temperature Range: –40°C to 85°C
- Available in 8-, 14-, 16-, 20-, 24-Pin TSSOP Package (All Pin-Compatible)
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Description
The CDCLVC11xx is a modular, high-performance, low-skew, general-purpose clock buffer family from Texas Instruments.
The entire family is designed with a modular approach in mind. It is intended to round up TIs series of LVCMOS clock generators.
Seven different fan-out variations, 1:2 to 1:12, are available. All of the devices are pin-compatible to each other for easy handling.
All family members share the same high performing characteristics such as low additive jitter, low skew, and wide operating temperature range.
The CDCLVC11xx supports an asynchronous output enable control (1G) which switches the outputs into a low state when 1G is low.
The CDCLVC11xx family operates in a 2.5-V and
3.3-V environment and are characterized for operation from –40°C to 85°C.
Similar but not functionally equivalent to the compared device:
Technical documentation
Type | Title | Date | |
---|---|---|---|
* | Datasheet | CDCLVC11xx 3.3-V and 2.5-V LVCMOS High-Performance Clock Buffer Family datasheet (Rev. B) | Feb. 24, 2017 |
Application note | How to Apply 1.8-V Signals to 3.3-V CDCLVC11xx Fanout Clock Buffer | Nov. 30, 2010 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
Description
Features
- Easy-to-use evaluation board to fan out low phase noise LVCMOS clock signals
- Easy device setup
- Enable pin configurable though jumper and SMA
- Board powered at 3.3V
Design tools & simulation
Features
- Leverages Cadence PSpice Technology
- Preinstalled library with a suite of digital models to enable worst-case timing analysis
- Dynamic updates ensure you have access to most current device models
- Optimized for simulation speed without loss of accuracy
- Supports simultaneous analysis of multiple products
- (...)
Reference designs
Design files
-
download TIDA-00209 BOMs.zip (210KB) -
download TIDA-00209 Assembly and Fabrication Files.zip (1471KB) -
download TIDA-00209 Layer Plots.zip (2388KB) -
download TIDA-00209 Altium Screenshots.zip (582KB) -
download TIDA-00209 Design Files.zip (9637KB)
CAD/CAE symbols
Package | Pins | Download |
---|---|---|
TSSOP (PW) | 16 | View options |
Ordering & quality
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
Recommended products may have parameters, evaluation modules or reference designs related to this TI product.
Support & training
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