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CDCLVP2104

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Low jitter, dual 1:4 universal-to-LVPECL buffer

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Data sheet

CDCLVP2104

ACTIVE
Data sheet Order now

Product details

Number of outputs 8 Additive RMS jitter (typ) (fs) 89 Core supply voltage (V) 2.5, 3.3 Output supply voltage (V) 2.5, 3.3 Output skew (ps) 15 Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVPECL Input type LVCMOS, LVDS, LVPECL
Number of outputs 8 Additive RMS jitter (typ) (fs) 89 Core supply voltage (V) 2.5, 3.3 Output supply voltage (V) 2.5, 3.3 Output skew (ps) 15 Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVPECL Input type LVCMOS, LVDS, LVPECL
VQFN (RHD) 28 25 mm² (5 mm × 5 mm)
  • Dual 1:4 Differential Buffer
  • Two Clock Inputs
  • Universal Inputs Can Accept LVPECL,
    LVDS, LVCMOS/LVTTL
  • Eight LVPECL Outputs
  • Maximum Clock Frequency: 2 GHz
  • Maximum Core Current Consumption: 78 mA
  • Very Low Additive Jitter: <100 fs,
    RMS in 10-kHz to 20-MHz Offset Range
  • 2.375-V to 3.6-V Device Power Supply
  • Maximum Propagation Delay: 450 ps
  • Maximum 15 ps Within Bank Output Skew
  • LVPECL Reference Voltage, VAC_REF,
    Available for Capacitive-Coupled Inputs
  • Industrial Temperature Range: –40°C to +85°C
  • Supports 105°C PCB Temperature (Measured with a Thermal Pad)
  • Available in 5-mm × 5-mm, 28-Pin VQFN (RHD) Package
  • ESD Protection Exceeds 2000 V (HBM)
  • Dual 1:4 Differential Buffer
  • Two Clock Inputs
  • Universal Inputs Can Accept LVPECL,
    LVDS, LVCMOS/LVTTL
  • Eight LVPECL Outputs
  • Maximum Clock Frequency: 2 GHz
  • Maximum Core Current Consumption: 78 mA
  • Very Low Additive Jitter: <100 fs,
    RMS in 10-kHz to 20-MHz Offset Range
  • 2.375-V to 3.6-V Device Power Supply
  • Maximum Propagation Delay: 450 ps
  • Maximum 15 ps Within Bank Output Skew
  • LVPECL Reference Voltage, VAC_REF,
    Available for Capacitive-Coupled Inputs
  • Industrial Temperature Range: –40°C to +85°C
  • Supports 105°C PCB Temperature (Measured with a Thermal Pad)
  • Available in 5-mm × 5-mm, 28-Pin VQFN (RHD) Package
  • ESD Protection Exceeds 2000 V (HBM)

The CDCLVP2104 is a highly versatile, low additive jitter buffer that can generate eight copies of LVPECL clock outputs from two LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. Each buffer block consists of one input that feeds two LVPECL outputs. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 15 ps, making the device a perfect choice for use in demanding applications.

The CDCLVP2104 clock buffer distributes two clock inputs (IN0, IN1) to eight pairs of differential LVPECL clock outputs (OUT0, OUT7) with minimum skew for clock distribution. Each buffer block consists of one input that feeds two LVPECL clock outputs. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.

The CDCLVP2104 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) must be applied to the unused negative input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.

The CDCLVP2104 is characterized for operation from &3150;40°C to +85°C and is available in a 5-mm × 5-mm, QFN-28 package.

The CDCLVP2104 is a highly versatile, low additive jitter buffer that can generate eight copies of LVPECL clock outputs from two LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. Each buffer block consists of one input that feeds two LVPECL outputs. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 15 ps, making the device a perfect choice for use in demanding applications.

The CDCLVP2104 clock buffer distributes two clock inputs (IN0, IN1) to eight pairs of differential LVPECL clock outputs (OUT0, OUT7) with minimum skew for clock distribution. Each buffer block consists of one input that feeds two LVPECL clock outputs. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.

The CDCLVP2104 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) must be applied to the unused negative input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.

The CDCLVP2104 is characterized for operation from &3150;40°C to +85°C and is available in a 5-mm × 5-mm, QFN-28 package.
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Technical documentation

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* Data sheet CDCLVP2104 Eight-LVPECL Output, High-Performance Clock Buffer datasheet (Rev. B) PDF | HTML Oct 25, 2013
User guide CDCLVP2104 User's Guide Oct 21, 2009

Design & development

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Evaluation board

CDCLVP2104EVM — CDCLVP2104 Evaluation Module

The CDCLVP2104 is a high-performance, low additive phase noise clock buffer. It has two universal input buffers that support either single-ended or differential clock inputs. Each input feeds a bank of four LVPECL outputs. The device also features on-chip bias generators that can provide the (...)
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CDCLVPxxxx IBIS Model (Rev. B)

SLLM056B.ZIP (40 KB) - IBIS model
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VQFN (RHD) 28 Ultra Librarian
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