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LMK1D1212

ACTIVE

12-channel output 1.8-V, 2.5-V, and 3.3-V LVDS buffer

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Data sheet

LMK1D1212

ACTIVE
Data sheet Order now

Product details

Function Clock buffer, Differential Additive RMS jitter (typ) (fs) 45 Output frequency (max) (MHz) 2000 Number of outputs 12 Output supply voltage (V) 1.8, 2.5, 3.3 Core supply voltage (V) 1.8, 2.5, 3.3 Output skew (ps) 20 Features 2:12 fanout, Universal inputs Operating temperature range (°C) -40 to 105 Rating Catalog Output type LVDS Input type HCSL, LP-HCSL, LVCMOS, LVDS, LVPECL
Function Clock buffer, Differential Additive RMS jitter (typ) (fs) 45 Output frequency (max) (MHz) 2000 Number of outputs 12 Output supply voltage (V) 1.8, 2.5, 3.3 Core supply voltage (V) 1.8, 2.5, 3.3 Output skew (ps) 20 Features 2:12 fanout, Universal inputs Operating temperature range (°C) -40 to 105 Rating Catalog Output type LVDS Input type HCSL, LP-HCSL, LVCMOS, LVDS, LVPECL
VQFN (RHA) 40 36 mm² 6 x 6
  • High-performance LVDS clock buffer family: up to 2 GHz
    • 2:12 differential buffer (LMK1D1212)
    • 2:16 differential buffer (LMK1D1216)
  • Supply voltage: 1.71 V to 3.465 V
  • Low additive jitter: < 60 fs RMS maximum in 12-kHz to 20-MHz at 156.25 MHz

    • Very low phase noise floor: -164 dBc/Hz (typical)

  • Very low propagation delay: < 575 ps maximum

  • Output skew: 20 ps maximum

  • High-swing LVDS (boosted mode): 500-mV VOD typical when AMP_SEL = 1
  • Universal inputs accept LVDS, LVPECL, LVCMOS, HCSL and CML signal levels
  • LVDS reference voltage, V AC_REF, available for capacitive-coupled inputs
  • Industrial temperature range: –40°C to 105°C
  • Packaged in

    • LMK1D1212: 6-mm × 6-mm, 40-pin VQFN (RHA)

    • LMK1D1216: 7-mm × 7-mm, 48-pin VQFN (RGZ)
  • High-performance LVDS clock buffer family: up to 2 GHz
    • 2:12 differential buffer (LMK1D1212)
    • 2:16 differential buffer (LMK1D1216)
  • Supply voltage: 1.71 V to 3.465 V
  • Low additive jitter: < 60 fs RMS maximum in 12-kHz to 20-MHz at 156.25 MHz

    • Very low phase noise floor: -164 dBc/Hz (typical)

  • Very low propagation delay: < 575 ps maximum

  • Output skew: 20 ps maximum

  • High-swing LVDS (boosted mode): 500-mV VOD typical when AMP_SEL = 1
  • Universal inputs accept LVDS, LVPECL, LVCMOS, HCSL and CML signal levels
  • LVDS reference voltage, V AC_REF, available for capacitive-coupled inputs
  • Industrial temperature range: –40°C to 105°C
  • Packaged in

    • LMK1D1212: 6-mm × 6-mm, 40-pin VQFN (RHA)

    • LMK1D1216: 7-mm × 7-mm, 48-pin VQFN (RGZ)

The LMK1D1212 clock buffer distributes with minimum skew one of two selectable clock inputs (IN0, IN1) to 12 pairs of differential LVDS clock outputs (OUT0 through OUT11). Similarly, the LMK1D1216 distributes 16 pairs of differential LVDS clock outputs (OUT0 through OUT15). The LMK1D121x family can accept two clock sources into an input multiplexer. The inputs can either be LVDS, LVPECL, LP-HCSL, HCSL, CML, or LVCMOS.

The LMK1D121x is specifically designed for driving 50-Ω transmission lines. When driving inputs in single-ended mode, apply the appropriate bias voltage to the unused negative input pin.

The IN_SEL pin selects the input which is routed to the outputs. If this pin is left open, it disables the outputs (static low). The part supports a fail-safe function. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

The device operates in 1.8-V or 2.5-V or 3.3-V supply environment and is characterized from –40°C to 105°C (ambient temperature).

The LMK1D1212 clock buffer distributes with minimum skew one of two selectable clock inputs (IN0, IN1) to 12 pairs of differential LVDS clock outputs (OUT0 through OUT11). Similarly, the LMK1D1216 distributes 16 pairs of differential LVDS clock outputs (OUT0 through OUT15). The LMK1D121x family can accept two clock sources into an input multiplexer. The inputs can either be LVDS, LVPECL, LP-HCSL, HCSL, CML, or LVCMOS.

The LMK1D121x is specifically designed for driving 50-Ω transmission lines. When driving inputs in single-ended mode, apply the appropriate bias voltage to the unused negative input pin.

The IN_SEL pin selects the input which is routed to the outputs. If this pin is left open, it disables the outputs (static low). The part supports a fail-safe function. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

The device operates in 1.8-V or 2.5-V or 3.3-V supply environment and is characterized from –40°C to 105°C (ambient temperature).
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* Data sheet LMK1D121x Low Additive Jitter LVDS Buffer datasheet (Rev. A) PDF | HTML 12 Apr 2023
User guide LMK1D1212EVM User's Guide PDF | HTML 26 Oct 2021

Design & development

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Evaluation board

LMK1D1212EVM — LMK1D1212 low jitter 2:12 LVDS fan-out buffer evaluation module

LMK1D1212 is a high-performance, low additive jitter LVDS clock buffer with two differential inputs and 12 LVDS outputs. This evaluation module (EVM) is designed to demonstrate the electrical performance of the LMK1D1212. This EVM can also be used to evaluate other 40 pin devices in the LMK1Dxxxx (...)
User guide: PDF | HTML
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Simulation model

LMK1DX IBIS Model (Rev. A)

SNAM251A.ZIP (55 KB) - IBIS Model
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PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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VQFN (RHA) 40 View options
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