Home Clocks & timing Clock buffers
Home
Clocks & timing
Clock buffers

LMK1D1204P

ACTIVE

4-channel output LVDS 1.8-V, 2.5-V, and 3.3-V buffer with pin control

Order now
Data sheet

LMK1D1204P

ACTIVE
Data sheet Order now

Product details

Number of outputs 4 Additive RMS jitter (typ) (fs) 50 Core supply voltage (V) 1.8, 2.5, 3.3 Output supply voltage (V) 1.8, 2.5, 3.3 Output skew (ps) 20 Operating temperature range (°C) -40 to 105 Rating Catalog Output type LVDS Input type HCSL, LP-HCSL, LVCMOS, LVDS, LVPECL
Number of outputs 4 Additive RMS jitter (typ) (fs) 50 Core supply voltage (V) 1.8, 2.5, 3.3 Output supply voltage (V) 1.8, 2.5, 3.3 Output skew (ps) 20 Operating temperature range (°C) -40 to 105 Rating Catalog Output type LVDS Input type HCSL, LP-HCSL, LVCMOS, LVDS, LVPECL
VQFN (RHD) 28 25 mm² 5 x 5
  • High-performance LVDS clock buffer family with 2 inputs and 4 outputs (2:4)
  • Output frequency up to 2 GHz
  • Hardware pins for individual output enable/disable
  • Supply voltage: 1.8 V / 2.5 V / 3.3 V ± 5%
  • Low additive jitter: < 60 fs rms maximum in 12 kHz to 20 MHz at 156.25 MHz

    • Very low phase noise floor: -164 dBc/Hz (typical)

  • Very low propagation delay: < 575 ps maximum

  • Output skew: 20 ps maximum

  • Fail-safe inputs
  • Universal inputs accept LVDS, LVPECL, LVCMOS, HCSL and CML
  • LVDS reference voltage, V AC_REF, available for capacitive-coupled inputs
  • Industrial temperature range: –40°C to 105°C
  • Packages available:
    • 5-mm × 5-mm, 28-pin VQFN (RHD)
  • High-performance LVDS clock buffer family with 2 inputs and 4 outputs (2:4)
  • Output frequency up to 2 GHz
  • Hardware pins for individual output enable/disable
  • Supply voltage: 1.8 V / 2.5 V / 3.3 V ± 5%
  • Low additive jitter: < 60 fs rms maximum in 12 kHz to 20 MHz at 156.25 MHz

    • Very low phase noise floor: -164 dBc/Hz (typical)

  • Very low propagation delay: < 575 ps maximum

  • Output skew: 20 ps maximum

  • Fail-safe inputs
  • Universal inputs accept LVDS, LVPECL, LVCMOS, HCSL and CML
  • LVDS reference voltage, V AC_REF, available for capacitive-coupled inputs
  • Industrial temperature range: –40°C to 105°C
  • Packages available:
    • 5-mm × 5-mm, 28-pin VQFN (RHD)

The LMK1D1204P clock buffer distributes one of two selectable clock inputs (IN0 and IN1) to 4 pairs of differential LVDS clock outputs (OUT0 through OUT3) with minimum skew for clock distribution. The inputs can be either LVDS, LVPECL, LVCMOS, HCSL, or CML.

The LMK1D1204P is specifically designed for driving 50-Ω transmission lines. When driving inputs in single-ended mode, apply the appropriate bias voltage to the unused negative input pin. The IN_SEL pin selects the input which is routed to the outputs. The part supports a fail-safe input function. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

Each LVDS differential output is enabled by setting the corresponding OEx pin to a logic high "1". If this pin is set to a logic low "0", the output is disabled in a high Z state resulting in reduced power consumption.

The device operates in a 1.8-V, 2.5-V, or 3.3-V supply environment and is characterized from –40°C to 105°C (ambient temperature).

The LMK1D1204P clock buffer distributes one of two selectable clock inputs (IN0 and IN1) to 4 pairs of differential LVDS clock outputs (OUT0 through OUT3) with minimum skew for clock distribution. The inputs can be either LVDS, LVPECL, LVCMOS, HCSL, or CML.

The LMK1D1204P is specifically designed for driving 50-Ω transmission lines. When driving inputs in single-ended mode, apply the appropriate bias voltage to the unused negative input pin. The IN_SEL pin selects the input which is routed to the outputs. The part supports a fail-safe input function. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

Each LVDS differential output is enabled by setting the corresponding OEx pin to a logic high "1". If this pin is set to a logic low "0", the output is disabled in a high Z state resulting in reduced power consumption.

The device operates in a 1.8-V, 2.5-V, or 3.3-V supply environment and is characterized from –40°C to 105°C (ambient temperature).
filter Find other Clock buffers
Download View video with transcript Video

Similar products you might be interested in

open-in-new Compare alternates
Similar functionality to the compared device
LMK1D1204 ACTIVE 4-channel output LVDS 1.8-V buffer Same performance without individual output enable/disable feature

Technical documentation

star =Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 1
Top documentation Type Title Format options Date
* Data sheet LMK1D1204P Pin-Controlled OE Low Additive Jitter LVDS Buffer datasheet (Rev. A) PDF | HTML 14 Jun 2023

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

LMK1D1208EVM — LMK1D1208 evaluation module for low jitter 2:8 LVDS fan-out buffer

LMK1D1208 is a high-performance, low additive jitter LVDS clock buffer with two differential inputs and eight LVDS outputs. This evaluation module (EVM) is designed to demonstrate the electrical performance of the LMK1D1208. This EVM can also be used to evaluate other 28-pin devices within the (...)
User guide: PDF | HTML
Not available on TI.com
Simulation model

LMK1DX IBIS Model (Rev. B)

SNAM251B.ZIP (67 KB) - IBIS Model
Download
Design tool

PLLATINUMSIM-SW — PLL loop filter, phase noise, lock time, and spur simulation tool

PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.

Supported products & hardware

Supported products & hardware
Download options
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Request
Package Pins CAD symbols, footprints & 3D models
VQFN (RHD) 28 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

TI E2E™ forums with technical support from TI engineers

View all forum topics

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos