Product details

Function Clock buffer, Differential Additive RMS jitter (Typ) (fs) 50 Output frequency (Max) (MHz) 2000 Number of outputs 4 Output supply voltage (V) 1.8, 2.5, 3.3 Core supply voltage (V) 1.8, 2.5, 3.3 Output skew (ps) 20 Features 2:4 fanout, Universal inputs, Individual output enable control, Pin control Operating temperature range (C) -40 to 105 Rating Catalog Output type LVDS Input type HCSL, LP-HCSL, LVCMOS, LVDS, LVPECL
Function Clock buffer, Differential Additive RMS jitter (Typ) (fs) 50 Output frequency (Max) (MHz) 2000 Number of outputs 4 Output supply voltage (V) 1.8, 2.5, 3.3 Core supply voltage (V) 1.8, 2.5, 3.3 Output skew (ps) 20 Features 2:4 fanout, Universal inputs, Individual output enable control, Pin control Operating temperature range (C) -40 to 105 Rating Catalog Output type LVDS Input type HCSL, LP-HCSL, LVCMOS, LVDS, LVPECL
VQFN (RHD) 28 25 mm² 5 x 5
  • High-performance LVDS clock buffer family with 2 inputs and 4 outputs (2:4).
  • Output frequency up to 2 GHz.
  • Hardware pins for individual output enable/disable.
  • Supply voltage: 1.8/2.5/3.3 V ± 5%
  • Low additive jitter: < 60 fs rms maximum in 12-kHz to 20-MHz @ 156.25 MHz
    • Very low phase noise floor: -164 dBc/Hz (typical)

  • Very low propagation delay: < 575 ps maximum

  • Output skew: 20 ps maximum

  • Universal inputs accept LVDS, LVPECL, LVCMOS, HCSL and CML
  • LVDS reference voltage, VAC_REF, available for capacitive-coupled inputs
  • Industrial temperature range: –40°C to 105°C
  • Packages available:
    • 5-mm × 5-mm, 28-pin VQFN (RHD)
  • High-performance LVDS clock buffer family with 2 inputs and 4 outputs (2:4).
  • Output frequency up to 2 GHz.
  • Hardware pins for individual output enable/disable.
  • Supply voltage: 1.8/2.5/3.3 V ± 5%
  • Low additive jitter: < 60 fs rms maximum in 12-kHz to 20-MHz @ 156.25 MHz
    • Very low phase noise floor: -164 dBc/Hz (typical)

  • Very low propagation delay: < 575 ps maximum

  • Output skew: 20 ps maximum

  • Universal inputs accept LVDS, LVPECL, LVCMOS, HCSL and CML
  • LVDS reference voltage, VAC_REF, available for capacitive-coupled inputs
  • Industrial temperature range: –40°C to 105°C
  • Packages available:
    • 5-mm × 5-mm, 28-pin VQFN (RHD)

The LMK1D1204P clock buffer distributes one of two selectable clock inputs (IN0 and IN1) to 4 pairs of differential LVDS clock outputs (OUT0 through OUT3) with minimum skew for clock distribution. The inputs can be either LVDS, LVPECL, LVCMOS, HCSL, or CML.

The LMK1D1204P is specifically designed for driving 50-Ω transmission lines. In case of driving the inputs in single-ended mode, the appropriate bias voltage as shown in Figure 8-6 must be applied to the unused negative input pin. The IN_SEL pin selects the input which is routed to the outputs. The part supports a fail-safe input function. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

Each LVDS differential output is enabled by setting the corresponding OEx pin to a logic high "1". If this pin is set to a logic low "0", the output is disabled in a high Z state resulting in reduced power consumption.

The device operates in 1.8-V or 2.5-V or 3.3-V supply environment and is characterized from –40°C to 105°C (ambient temperature).

The LMK1D1204P clock buffer distributes one of two selectable clock inputs (IN0 and IN1) to 4 pairs of differential LVDS clock outputs (OUT0 through OUT3) with minimum skew for clock distribution. The inputs can be either LVDS, LVPECL, LVCMOS, HCSL, or CML.

The LMK1D1204P is specifically designed for driving 50-Ω transmission lines. In case of driving the inputs in single-ended mode, the appropriate bias voltage as shown in Figure 8-6 must be applied to the unused negative input pin. The IN_SEL pin selects the input which is routed to the outputs. The part supports a fail-safe input function. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

Each LVDS differential output is enabled by setting the corresponding OEx pin to a logic high "1". If this pin is set to a logic low "0", the output is disabled in a high Z state resulting in reduced power consumption.

The device operates in 1.8-V or 2.5-V or 3.3-V supply environment and is characterized from –40°C to 105°C (ambient temperature).

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* Data sheet LMK1D1204P Pin-Controlled OE Low Additive Jitter LVDS Buffer datasheet 29 Sep 2021

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Evaluation board

LMK1D1208EVM — LMK1D1208 low jitter 2:8 LVDS fan-out buffer evaluation module

LMK1D1208 is a high-performance, low additive jitter LVDS clock buffer with two differential inputs and eight LVDS outputs. This evaluation module (EVM) is designed to demonstrate the electrical performance of the LMK1D1208. This EVM can also be used to evaluate other 28-pin devices within the (...)
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SNAM251A.ZIP (55 KB) - IBIS Model
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PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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VQFN (RHD) 28 View options

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