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CDCLVD2104

ACTIVE

Low jitter, dual 1:4 universal-to-LVDS buffer

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Data sheet

CDCLVD2104

ACTIVE
Data sheet Order now

Product details

Function Differential Additive RMS jitter (typ) (fs) 171 Output frequency (max) (MHz) 800 Number of outputs 8 Output supply voltage (V) 2.5 Core supply voltage (V) 2.5 Output skew (ps) 35 Features Dual 1:4 fanout, Output enable control, Universal inputs Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVDS Input type LVCMOS, LVDS, LVPECL
Function Differential Additive RMS jitter (typ) (fs) 171 Output frequency (max) (MHz) 800 Number of outputs 8 Output supply voltage (V) 2.5 Core supply voltage (V) 2.5 Output skew (ps) 35 Features Dual 1:4 fanout, Output enable control, Universal inputs Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVDS Input type LVCMOS, LVDS, LVPECL
VQFN (RHD) 28 25 mm² 5 x 5
  • Dual 1:4 Differential Buffer
  • Low Additive Jitter <300 fs, RMS in
    10 kHz to 20 MHz
  • Low Within Bank Output Skew of 35ps (Max)
  • Universal Inputs Accept LVDS, LVPECL, LVCMOS
  • One Input Dedicated for Four Output Buffers
  • 8 LVDS Outputs, ANSI EIA/TIA-644A Standard Compatible
  • Clock Frequency up to 800 MHz
  • 2.375–2.625V Device Power Supply
  • LVDS Reference Voltage, VAC_REF, Available for Capacitive Coupled Inputs
  • Industrial Temperature Range –40°C to 85°C
  • Packaged in 5mm × 5mm 28-Pin QFN (RHD)
  • ESD Protection Exceeds 3 kV HBM, 1 kV CDM
  • APPLICATIONS
    • Telecommunications/Networking
    • Medical Imaging
    • Test and Measurement Equipment
    • Wireless Communications
    • General Purpose Clocking
  • Dual 1:4 Differential Buffer
  • Low Additive Jitter <300 fs, RMS in
    10 kHz to 20 MHz
  • Low Within Bank Output Skew of 35ps (Max)
  • Universal Inputs Accept LVDS, LVPECL, LVCMOS
  • One Input Dedicated for Four Output Buffers
  • 8 LVDS Outputs, ANSI EIA/TIA-644A Standard Compatible
  • Clock Frequency up to 800 MHz
  • 2.375–2.625V Device Power Supply
  • LVDS Reference Voltage, VAC_REF, Available for Capacitive Coupled Inputs
  • Industrial Temperature Range –40°C to 85°C
  • Packaged in 5mm × 5mm 28-Pin QFN (RHD)
  • ESD Protection Exceeds 3 kV HBM, 1 kV CDM
  • APPLICATIONS
    • Telecommunications/Networking
    • Medical Imaging
    • Test and Measurement Equipment
    • Wireless Communications
    • General Purpose Clocking

The CDCLVD2104 clock buffer distributes two clock inputs (IN0, IN1) to a total of 8 pairs of differential LVDS clock outputs (OUT0, OUT7). Each buffer block consists of one input and 4 LVDS outputs. The inputs can either be LVDS, LVPECL, or LVCMOS.

The CDCLVD2104 is specifically designed for driving 50- transmission lines. If the input is in single ended mode, the appropriate bias voltage (VAC_REF) should be applied to the unused negative input pin.

Using the control pin (EN), outputs can be either disabled or enabled. If the EN pin is left open two buffers with all outputs are enabled, if switched to a logical "0" both buffers with all outputs are disabled (static logical “0”), if switched to a logical "1", one buffer with four outputs is disabled and another buffer with four outputs is enabled. The part supports a fail safe function. It incorporates an input hysteresis, which prevents random oscillation of the outputs in absence of an input signal.

The device operates in 2.5V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD2104 is packaged in small 28-pin, 5-mm × 5-mm QFN package.

The CDCLVD2104 clock buffer distributes two clock inputs (IN0, IN1) to a total of 8 pairs of differential LVDS clock outputs (OUT0, OUT7). Each buffer block consists of one input and 4 LVDS outputs. The inputs can either be LVDS, LVPECL, or LVCMOS.

The CDCLVD2104 is specifically designed for driving 50- transmission lines. If the input is in single ended mode, the appropriate bias voltage (VAC_REF) should be applied to the unused negative input pin.

Using the control pin (EN), outputs can be either disabled or enabled. If the EN pin is left open two buffers with all outputs are enabled, if switched to a logical "0" both buffers with all outputs are disabled (static logical “0”), if switched to a logical "1", one buffer with four outputs is disabled and another buffer with four outputs is enabled. The part supports a fail safe function. It incorporates an input hysteresis, which prevents random oscillation of the outputs in absence of an input signal.

The device operates in 2.5V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD2104 is packaged in small 28-pin, 5-mm × 5-mm QFN package.
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Type Title Date
* Data sheet Dual 1:4 Low Additive Jitter LVDS Buffer datasheet (Rev. A) 31 Aug 2010

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

CDCLVD2102EVM — CDCLVD2102 Evaluation Module

The CDCLVD1204/CDCLVD2102 are high-performance, low-additive jitter clock buffers. They have twouniversal input buffers that support single-ended or differential clock inputs and are selectable through a control pin (for CDCLVD1204 only). The devices also feature on-chip bias generators that can (...)
User guide: PDF
Not available on TI.com
Simulation model

CDCLVD2104 IBIS Model (Rev. B)

SLLM094B.ZIP (14 KB) - IBIS Model
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Design tool

CLOCK-TREE-ARCHITECT — Clock tree architect programming software

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
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Design tool

PLLATINUMSIM-SW — PLLatinum Sim Tool

PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.

Supported products & hardware

Supported products & hardware

Products
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CDCDB2000 — DB2000QL compliant 20-output clock buffer for PCIe® Gen 1 to Gen 5 CDCDB400 — 4-output clock buffer for PCIe® Gen 1 to Gen 6 CDCDB800 — 8-output clock buffer for PCIe® Gen 1 to Gen 6 CDCDB803 — 8-output clock buffer for PCIe® Gen 1 to Gen 6 with selectable SMBus addresses CDCLVC1102 — Low jitter, 1:2 LVCMOS fan-out clock buffer CDCLVC1103 — Low jitter, 1:3 LVCMOS fan-out clock buffer CDCLVC1104 — Low jitter, 1:4 LVCMOS fan-out clock buffer CDCLVC1106 — Low jitter, 1:6 LVCMOS fan-out clock buffer CDCLVC1108 — Low jitter, 1:8 LVCMOS fan-out clock buffer CDCLVC1110 — Low jitter, 1:10 LVCMOS fan-out clock buffer CDCLVC1112 — Low jitter, 1:12 LVCMOS fan-out clock buffer CDCLVC1310 — Universal input, 10-output low impedance LVCMOS buffer CDCLVD110A — 1-to-10 LVDS clock buffer up to 1100-MHz with minimum skew for clock distribution CDCLVD1204 — Low jitter, 2-input selectable 1:4 universal-to-LVDS buffer CDCLVD1208 — Low jitter, 2-input selectable 1:8 universal-to-LVDS buffer CDCLVD1212 — Low jitter, 2-input selectable 1:12 universal-to-LVDS buffer CDCLVD1213 — Low jitter, 1:4 universal-to-LVDS buffer with selectable output divider CDCLVD1216 — Low jitter, 2-input selectable 1:16 universal-to-LVDS buffer CDCLVD2102 — Low jitter, dual 1:2 universal-to-LVDS buffer CDCLVD2104 — Low jitter, dual 1:4 universal-to-LVDS buffer CDCLVD2106 — Low jitter, dual 1:6 universal-to-LVDS buffer CDCLVD2108 — Low jitter, dual 1:8 universal-to-LVDS buffer CDCLVP110 — 1:10 LVPECL/HSTL to LVPECL clock driver CDCLVP1102 — Low jitter 1:2 universal-to-LVPECL buffer CDCLVP111 — 1:10 LVPECL buffer with selectable input CDCLVP111-EP — HiRel, 1:10 LVPECL buffer with selectable input CDCLVP111-SP — 1:10 high speed clock buffer with selectable input clock driver CDCLVP1204 — Low-jitter, two-input, selectable 1:4 universal-to-LVPECL buffer CDCLVP1208 — Low jitter, 2-input selectable 1:8 universal-to-LVPECL buffer CDCLVP1212 — Low jitter, 2-input selectable 1:12 universal-to-LVPECL buffer CDCLVP1216 — Low jitter, 2-input selectable 1:16 universal-to-LVPECL buffer CDCLVP2102 — Low jitter, dual 1:2 universal-to-LVPECL buffer CDCLVP2104 — Low jitter, dual 1:4 universal-to-LVPECL buffer CDCLVP2106 — Low jitter, dual 1:6 universal-to-LVPECL buffer CDCLVP2108 — Low jitter, dual 1:8 universal-to-LVPECL buffer CDCLVP215 — Dual 1:5 high speed LVPECL fan out buffer LMK00301 — 3-GHz, 10-output differential fanout buffer / level translator LMK00304 — 3.1-GHz differential clock buffer/level translator with 4 configurable outputs LMK00306 — 3.1-GHz differential clock buffer/level translator with 6 configurable outputs LMK00308 — 3.1-GHz differential clock buffer/level translator with 8 configurable outputs LMK00334 — 4-output PCIe® Gen1/Gen2/Gen3/Gen4/Gen5 clock buffer and level translator LMK00334-Q1 — Automotive 4-output PCIe® Gen1/Gen2/Gen3/Gen4/Gen5 clock buffer and level translator LMK00338 — 8-output PCIe® Gen1/Gen2/Gen3/Gen4/Gen5 clock buffer and level translator LMK1C1102 — 2-channel output LVCMOS 1.8-V buffer LMK1C1103 — 3-channel output LVCMOS 1.8-V buffer LMK1C1104 — 4-channel output LVCMOS 1.8-V buffer LMK1C1106 — 6-channel output LVCMOS 1.8-V buffer LMK1C1108 — 8-channel output LVCMOS 1.8-V buffer LMK1D1204 — 4-channel output LVDS 1.8-V buffer LMK1D1204P — 4-channel output LVDS 1.8-V, 2.5-V, and 3.3-V buffer with pin control LMK1D1208 — 8-channel output LVDS 1.8-V, 2.5-V, and 3.3-V buffer LMK1D1208I — 8-channel output, 1.8-V, 2.5-V, and 3.3-V LVDS buffer with I²C LMK1D1208P — 8-channel output 1.8-V, 2.5-V, and 3.3-V LVDS buffer with pin control LMK1D1212 — 12-channel output 1.8-V, 2.5-V, and 3.3-V LVDS buffer LMK1D1216 — 16-channel output 1.8-V, 2.5-V, and 3.3-V LVDS buffer LMK1D2102 — Dual bank 2-channel output LVDS 1.8-V, 2.5-V, and 3.3-V buffer LMK1D2102L — Low additive jitter LVDS buffer LMK1D2104 — Dual bank 4-channel output 1.8V, 2.5V and 3.3V LVDS buffer LMK1D2104L — Dual bank 4-channel output LVDS 1.8V, 2.5V, and 3.3V buffer with 0.7V output common mode option LMK1D2106 — Dual bank 6-channel output 1.8-V, 2.5-V, and 3.3-V LVDS buffer LMK1D2106L — Dual bank 2-channel output LVDS 1.8V, 2.5V and 3.3V buffer with 0.7V output common mode option LMK1D2108 — Dual bank 8-channel output 1.8-V, 2.5-V, and 3.3-V LVDS buffer
Clock generators
LMK03318 — Ultra-low jitter clock generator family with single PLL LMK03328 — Ultra-low jitter clock generator family with two independent PLLs LMK3C0105 — 5 output reference-less clock generator with bulk acoustic wave (BAW) LMK3C0105-Q1 — Automotive, 5 output reference-less clock generator with bulk acoustic wave (BAW) LMK3H0102 — Bulk acoustic wave (BAW)-based PCIe Gen 1 to Gen 7-compliant referenceless clock generator LMK3H0102-Q1 — Automotive PCIe gen 7 compliant, reference-less clock generator with bulk acoustic wave (BAW)
Clock jitter cleaners
LMK04803 — Low-noise clock jitter cleaner with dual cascaded PLLs and integrated 1.9-GHz VCO LMK04805 — Low-noise clock jitter cleaner with dual cascaded PLLs and integrated 2.2-GHz VCO LMK04806 — Low-noise clock jitter cleaner with dual cascaded PLLs and integrated 2.5-GHz VCO LMK04808 — Low-noise clock jitter cleaner with dual loop PLLs and integrated 2.9-GHz VCO LMK04816 — Three input low-noise clock jitter cleaner with dual loop PLLs LMK04821 — Ultra low jitter synthesizer and jitter cleaner with JESD204B support LMK04826 — Ultra low-noise JESD204B compliant clock jitter cleaner with integrated 1840 to1970-MHz VCO0 LMK04828 — Ultra low-noise JESD204B compliant clock jitter cleaner with integrated 2370 to 2630-MHz VCO0. LMK04828-EP — Ultra low-noise JESD204B compliant clock jitter cleaner with temperature range -55 to 105c LMK04832 — Ultra-low-noise, 3.2-GHz, 15-output, JESD204B clock jitter cleaner with dual loop LMK04832-SEP — Radiation-tolerant, 30-krad, ultra-low-noise, 3.2-GHz 15-output JESD204C clock jitter cleaner LMK04832-SP — Radiation-hardened-assured (RHA), ultra-low-noise, 3.2-GHz, 15-output clock jitter cleaner
Oscillators
LMK60A0-148351 — 148.352-MHz, LVDS, high-performance, low jitter, differential oscillator LMK60A0-148M — 148.5-MHz, LVDS, high-performance, low jitter, differential oscillator LMK60E0-156257 — 156.257-MHz, LVPECL, ±25 ppm, high-performance, low-jitter oscillator LMK60E0-156M — 156.5-MHz, LVPECL, ±25 ppm, high-performance, low-jitter oscillator LMK60E0-212M — 212.5-MHz, LVPECL, ±25 ppm, high-performance, low-jitter oscillator LMK60E2-100M — 100.0-MHz, LVPECL, ±50 ppm, high-performance, low-jitter oscillator LMK60E2-125M — 125-MHz, LVPECL, ±50 ppm, high-performance, low-jitter oscillator LMK60E2-150M — 150-MHz, LVPECL, ±50 ppm, low jitter, standard oscillator LMK60E2-156M — 156.25-MHz, LVPECL, ±50 ppm, high-performance, low-jitter oscillator LMK60I2-100M — 100-MHz, HCSL, ±50 ppm, high-performance, low-jitter oscillator LMK60I2-322M — 322.27-MHz, HCSL, ±50 ppm, high-performance, low-jitter oscillator LMK61A2-100M — 100-MHz, ±50 ppm, LVDS ultra-low jitter standard differential oscillator LMK61A2-125M — 125-MHz, ±50 ppm, LVDS ultra-low jitter standard differential oscillator LMK61A2-156M — 156.25-MHz, ±50 ppm, LVDS ultra-low jitter standard differential oscillator LMK61A2-312M — 312.5-MHz, ±50 ppm, LVDS ultra-low jitter standard differential oscillator LMK61A2-644M — LVDS ultra-low jitter programmable oscillator with internal EEPROM LMK61E0-050M — 50-MHz, LVPECL ±25 ppm, ultra-low jitter, standard differential oscillator LMK61E0-155M — 155.52-MHz, LVPECL ±25 ppm, ultra-low jitter, standard differential oscillator LMK61E0-156M — 156.25-MHz, ±25 ppm, LVPECL ultra-low jitter standard differential oscillator LMK61E07 — Multi-signal format, ultra-low jitter programmable oscillator with internal EEPROM LMK61E08 — Ultra-low jitter programmable oscillator with internal EEPROM LMK61E0M — LVCMOS ultra-low jitter programmable oscillator with internal EEPROM LMK61E2 — Ultra-low jitter, EEPROM programmable oscillator for medical imaging and test and measurement LMK61E2-100M — 100-MHz, ±50 ppm, LVPECL ultra-low jitter standard differential oscillator LMK61E2-125M — 125-MHz, ±50 ppm, LVPECL ultra-low jitter standard differential oscillator LMK61E2-156M — 156.25-MHz, ±50 ppm, LVPECL ultra-low jitter standard differential oscillator LMK61E2-312M — 312.5-MHz, ±50 ppm, LVPECL ultra-low jitter standard differential oscillator LMK61I2-100M — 100-MHz, ±50 ppm, HCSL ultra-low jitter standard differential oscillator LMK61PD0A2 — ±50 ppm, ultra-low jitter, pin selectable, differential oscillator LMK62A2-100M — 100-MHz, LVDS ±50 ppm, high-performance, low-jitter, standard oscillator LMK62A2-150M — 150-MHz, LVDS ±50 ppm, high-performance, low-jitter, standard oscillator LMK62A2-156M — 156.25-MHz, LVDS ±50 ppm, high-performance, low-jitter oscillator LMK62A2-200M — 200-MHz, LVDS ±50 ppm, high-performance, low-jitter, standard oscillator LMK62A2-266M — 266.66-MHz, LVDS ±50 ppm, high-performance, low-jitter, standard oscillator LMK62E0-156M — 156.25-MHz, LVPECL, ±25 ppm, high-performance, low-jitter oscillator LMK62E2-100M — 100-MHz, LVPECL, ±50 ppm, high-performance, low-jitter oscillator LMK62E2-156M — 156.25-MHz, LVPECL, ±50 ppm, high-performance, low jitter, standard oscillator LMK62I0-100M — 100-MHz, HCSL, ±25 ppm, high-performance, low-jitter oscillator LMK62I0-156M — 156.25-MHz, HCSL, ±25 ppm, high-performance, low-jitter oscillator LMK6C — Low-jitter, high-performance, bulk-acoustic-wave (BAW) fixed-frequency LVCMOS oscillator LMK6D — Low-jitter, high-performance, bulk-acoustic-wave (BAW) fixed-frequency LVDS oscillator LMK6H — Low-jitter, high-performance, bulk-acoustic-wave (BAW) fixed-frequency HCSL oscillator LMK6P — Low-jitter, high-performance, bulk-acoustic-wave (BAW) fixed-frequency LVPECL oscillator
Hardware development
Evaluation board
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Software
Support software
LMX9830-SW — LMX9830 Application Notes, Software, and Tools LMX9838-SW — LMX9838 Application Notes, Software, and Tools
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Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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