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CDCLVD2106

ACTIVE

Low jitter, dual 1:6 universal-to-LVDS buffer

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Data sheet

CDCLVD2106

ACTIVE
Data sheet Order now

Product details

Number of outputs 12 Additive RMS jitter (typ) (fs) 171 Core supply voltage (V) 2.5 Output supply voltage (V) 2.5 Output skew (ps) 45 Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVDS Input type LVCMOS, LVDS, LVPECL
Number of outputs 12 Additive RMS jitter (typ) (fs) 171 Core supply voltage (V) 2.5 Output supply voltage (V) 2.5 Output skew (ps) 45 Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVDS Input type LVCMOS, LVDS, LVPECL
VQFN (RHA) 40 36 mm² (6 mm × 6 mm)
  • Dual 1:6 Differential Buffer
  • Low Additive Jitter: <300 fs rms
    in 10 kHz – 20 MHz
  • Low Within Bank Output Skew of 45 ps (Max)
  • Universal Inputs Accept LVDS, LVPECL, LVCMOS
  • One Input Dedicated for Six Outputs
  • Total of 12 LVDS Outputs, ANSI EIA/TIA-644A Standard Compatible
  • Clock Frequency up to 800 MHz
  • 2.375–2.625 V Device Power Supply
  • LVDS Reference Voltage, VAC_REF,
    Available for Capacitive Coupled Inputs
  • Industrial Temperature Range –40°C to 85°C
  • Packaged in 6 mm × 6 mm 40-pin QFN (RHA)
  • ESD Protection Exceeds 3-kV HBM, 1-kV CDM
  • APPLICATIONS
    • Telecommunications/Networking
    • Medical Imaging
    • Test and Measurement Equipment
    • Wireless Communications
    • General Purpose Clocking
  • Dual 1:6 Differential Buffer
  • Low Additive Jitter: <300 fs rms
    in 10 kHz – 20 MHz
  • Low Within Bank Output Skew of 45 ps (Max)
  • Universal Inputs Accept LVDS, LVPECL, LVCMOS
  • One Input Dedicated for Six Outputs
  • Total of 12 LVDS Outputs, ANSI EIA/TIA-644A Standard Compatible
  • Clock Frequency up to 800 MHz
  • 2.375–2.625 V Device Power Supply
  • LVDS Reference Voltage, VAC_REF,
    Available for Capacitive Coupled Inputs
  • Industrial Temperature Range –40°C to 85°C
  • Packaged in 6 mm × 6 mm 40-pin QFN (RHA)
  • ESD Protection Exceeds 3-kV HBM, 1-kV CDM
  • APPLICATIONS
    • Telecommunications/Networking
    • Medical Imaging
    • Test and Measurement Equipment
    • Wireless Communications
    • General Purpose Clocking

The CDCLVD2106 clock buffer distributes two clock inputs (IN0, IN1) to a total of 12 pairs of differential LVDS clock outputs (OUT0, OUT11). Each buffer block consists of one input and 6 LVDS outputs. The inputs can either be LVDS, LVPECL, or LVCMOS.

The CDCLVD2106 is specifically designed for driving 50-Ω transmission lines. In case of driving the inputs in single ended mode, the appropriate bias voltage (VAC_REF) should be applied to the unused negative input pin.

Using the control pin (EN), outputs can be either disabled or enabled. If the EN pin is left open two buffers with all outputs are enabled, if switched to a logical "0" both buffers with all outputs are disabled (static logical "0"), if switched to a logical "1", one buffer with six outputs is disabled and another buffer with six outputs is enabled. The part supports a fail safe function. It incorporates an input hysteresis, which prevents random oscillation of the outputs in absence of an input signal.

The device operates in 2.5V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD2106 is packaged in small 40-pin, 6-mm × 6-mm QFN package.

The CDCLVD2106 clock buffer distributes two clock inputs (IN0, IN1) to a total of 12 pairs of differential LVDS clock outputs (OUT0, OUT11). Each buffer block consists of one input and 6 LVDS outputs. The inputs can either be LVDS, LVPECL, or LVCMOS.

The CDCLVD2106 is specifically designed for driving 50-Ω transmission lines. In case of driving the inputs in single ended mode, the appropriate bias voltage (VAC_REF) should be applied to the unused negative input pin.

Using the control pin (EN), outputs can be either disabled or enabled. If the EN pin is left open two buffers with all outputs are enabled, if switched to a logical "0" both buffers with all outputs are disabled (static logical "0"), if switched to a logical "1", one buffer with six outputs is disabled and another buffer with six outputs is enabled. The part supports a fail safe function. It incorporates an input hysteresis, which prevents random oscillation of the outputs in absence of an input signal.

The device operates in 2.5V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD2106 is packaged in small 40-pin, 6-mm × 6-mm QFN package.
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* Data sheet Dual 1:6 Low Additive Jitter LVDS Buffer datasheet (Rev. B) Jan 17, 2011

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

CDCLVD2106EVM — CDCLVD2106 Evaluation Module

The CDCLVD1212/CDCLVD2106 are high-performance, low-additive jitter clock buffers. They have two universal input buffers that support single-ended or differential clock inputs and are selectable through a control pin (for CDCLVD1212 only). The devices also feature on-chip bias generators that can (...)
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Simulation model

CDCLVD2106 IBIS Model (Rev. B)

SLLM095B.ZIP (15 KB) - IBIS model
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CLOCK-TREE-ARCHITECT — Clock tree architect programming software

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.

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PLLATINUMSIM-SW — PLL loop filter, phase noise, lock time, and spur simulation tool

PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.

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VQFN (RHA) 40 Ultra Librarian
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