The CDCLVP110 clock driver distributes one differential clock pair of either LVPECL or HSTL (selectable) input, (CLK0, CLK1) to ten pairs of differential LVPECL clock (Q0, Q9) outputs with minimum skew for clock distribution. The CDCLVP110 can accept two clock sources into an input multiplexer. The CLK0 input accepts either LVECL/LVPECL input signals, while CLK1 accepts an HSTL input signal when operated under LVPECL conditions. The CDCLVP110 is specifically designed for driving 50-Ω transmission lines.
The VBB reference voltage output is used if single-ended input operation is required. In this case the VBB pin should be connected to CLK0 and bypassed to GND via a 10-nF capacitor.
However, for high-speed performance up to 3.5 GHz, the differential mode is strongly recommended.
The CDCLVP110 is characterized for operation from –40°C to 85°C.
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Data sheet | Low-Voltage 1:10 LVPECL/HSTL With Selectable Input Clock Driver datasheet (Rev. D) | Jan 11, 2011 | |
| Application note | Clocking Design Guidelines: Unused Pins | Nov 19, 2015 | ||
| Application note | AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C) | Oct 17, 2007 | ||
| Application note | Advantage of Using TI's Lowest Jitter Differential Clock Buffer | Aug 20, 2003 | ||
| Application note | DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CML | Feb 19, 2003 | ||
| Application note | PCB Layout Guidelines for CDCLVP110 | Jun 12, 2002 |
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| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| LQFP (VF) | 32 | Ultra Librarian |
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