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Product details

Parameters

Function Differential Additive RMS jitter (Typ) (fs) 300 Output frequency (Max) (MHz) 3500 Number of outputs 10 Output supply voltage (V) 2.5, 3.3 Core supply voltage (V) 2.5, 3.3 Output skew (ps) 30 Features 1:10 fanout Operating temperature range (C) -40 to 85 Rating Catalog Output type LVPECL Input type HSTL, LVPECL open-in-new Find other Clock buffers

Package | Pins | Size

LQFP (VF) 32 49 mm² 7 x 7 open-in-new Find other Clock buffers

Features

  • Distributes One Differential Clock Input Pair
    LVPECL/HSTL to 10 Differential LVPECL Clock Outputs
  • Fully Compatible With LVECL/LVPECL/HSTL
  • Single Supply Voltage Required, ±3.3-V or ±2.5-V Supply
  • Selectable Clock Input Through CLK_SEL
  • Low-Output Skew (Typ 15 ps) for Clock-Distribution Applications
  • VBB Reference Voltage Output for Single-Ended Clocking
  • Available in a 32-Pin LQFP Package
  • Frequency Range From DC to 3.5 GHz
  • Pin-to-Pin Compatible With MC100 Series EP111, ES6111, LVEP111, PTN1111

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Description

The CDCLVP110 clock driver distributes one differential clock pair of either LVPECL or HSTL (selectable) input, (CLK0, CLK1) to ten pairs of differential LVPECL clock (Q0, Q9) outputs with minimum skew for clock distribution. The CDCLVP110 can accept two clock sources into an input multiplexer. The CLK0 input accepts either LVECL/LVPECL input signals, while CLK1 accepts an HSTL input signal when operated under LVPECL conditions. The CDCLVP110 is specifically designed for driving 50-Ω transmission lines.

The VBB reference voltage output is used if single-ended input operation is required. In this case the VBB pin should be connected to CLK0 and bypassed to GND via a 10-nF capacitor.

However, for high-speed performance up to 3.5 GHz, the differential mode is strongly recommended.

The CDCLVP110 is characterized for operation from –40°C to 85°C.

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Technical documentation

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Type Title Date
* Datasheet Low-Voltage 1:10 LVPECL/HSTL With Selectable Input Clock Driver datasheet (Rev. D) Jan. 11, 2011
Application notes Clocking Design Guidelines: Unused Pins Nov. 19, 2015
Application notes AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C) Oct. 17, 2007
Application notes Advantage of Using TI's Lowest Jitter Differential Clock Buffer Aug. 20, 2003
Application notes DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CML Feb. 19, 2003
Application notes PCB Layout Guidelines for CDCLVP110 Jun. 12, 2002

Design & development

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LQFP (VF) 32 View options

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