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|*||Data sheet||Low-Voltage 1:10 LVPECL/HSTL With Selectable Input Clock Driver datasheet (Rev. D)||11 Jan 2011|
|Application note||Clocking Design Guidelines: Unused Pins||19 Nov 2015|
|Application note||AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C)||17 Oct 2007|
|Application note||Advantage of Using TI's Lowest Jitter Differential Clock Buffer||20 Aug 2003|
|Application note||DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CML||19 Feb 2003|
|Application note||PCB Layout Guidelines for CDCLVP110||12 Jun 2002|
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|LQFP (VF)||32||View options|
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