Low Jitter, 2-Input Selectable 1:16 Universal-to-LVDS Buffer


Product details


Function Differential Additive RMS jitter (Typ) (fs) 171 Output frequency (Max) (MHz) 800 Number of outputs 16 VCC out (V) 2.5 VCC core (V) 2.5 Output skew (ps) 55 Features 2:16 fanout, Universal inputs Operating temperature range (C) -40 to 85 Rating Catalog Output type LVDS Input type LVCMOS, LVDS, LVPECL open-in-new Find other Clock buffers

Package | Pins | Size

VQFN (RGZ) 48 49 mm² 7 x 7 open-in-new Find other Clock buffers


  • 2:16 Differential Buffer
  • Low Additive Jitter: <300 fs RMS in
    10 kHz to 20 MHz
  • Low Output Skew of 55 ps (Max)
  • Universal Inputs Accept LVDS, LVPECL, LVCMOS
  • Selectable Clock Inputs Through Control Pin
  • 16 LVDS Outputs, ANSI EIA/TIA-644A Standard Compatible
  • Clock Frequency up to 800 MHz
  • 2.375–2.625V Device Power Supply
  • LVDS Reference Voltage, VAC_REF,
    Available for Capacitive Coupled Inputs
  • Industrial Temperature Range –40°C to 85°C
  • Packaged in 7mm × 7mm 48-Pin QFN (RGZ)
  • ESD Protection Exceeds 3 kV HBM, 1 kV CDM
    • Telecommunications/Networking
    • Medical Imaging
    • Test and Measurement Equipment
    • Wireless Communications
    • General Purpose Clocking

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The CDCLVD1216 clock buffer distributes one of two selectable clock inputs (IN0, IN1) to 16 pairs of differential LVDS clock outputs (OUT0, OUT15) with minimum skew for clock distribution. The CDCLVD1216 can accept two clock sources into an input multiplexer. The inputs can either be LVDS, LVPECL, or LVCMOS.

The CDCLVD1216 is specifically designed for driving 50 Ω transmission lines. If driving the inputs in single ended mode, the appropriate bias voltage (VAC_REF) should be applied to the unused negative input pin.

The IN_SEL pin selects the input which is routed to the outputs. If this pin is left open it disables the outputs (static). The part supports a fail safe function. It incorporates an input hysteresis, which prevents random oscillation of the outputs in absence of an input signal.

The device operates in 2.5 V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD1216 is packaged in small 48-pin, 7mm × 7mm QFN package.

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LMK00301 ACTIVE 3-GHz, 10-Output Differential Fanout Buffer / Level Translator Ultra low additive jitter,1:10 Universal Differential Buffer that can support LVDS

Technical documentation

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Type Title Date
* Datasheet 2:16 Low Additive Jitter LVDS Buffer datasheet (Rev. B) Jan. 17, 2011
Selection guides Clock & Timing Solutions (Rev. C) Jan. 19, 2017

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

The CDCLVD1212/CDCLVD2106 are high-performance, low-additive jitter clock buffers. They have two universal input buffers that support single-ended or differential clock inputs and are selectable through a control pin (for CDCLVD1212 only). The devices also feature on-chip bias generators that can (...)
  • Easy-to-use evaluation board to fan out low-phase noise clocks
  • Easy device setup
  • Fast configuration
  • Control pins configurable through jumpers
  • Board powered at 2.5 V
  • Single-ended or differential input clocks
  • Device supports twelve LVDS outputs, EVM supports four LVDS outputs

Design tools & simulation

SLLM092C.ZIP (15 KB) - IBIS Model

CAD/CAE symbols

Package Pins Download
VQFN (RGZ) 48 View options

Ordering & quality

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