CDCLVD2108

ACTIVE

Low Jitter, Dual 1:8 Universal-to-LVDS Buffer

Top

Product details

Parameters

Function Differential Additive RMS jitter (Typ) (fs) 171 Output frequency (Max) (MHz) 800 Number of outputs 16 Output supply voltage (V) 2.5 Core supply voltage (V) 2.5 Output skew (ps) 50 Features Dual 1:8 fanout, Universal inputs, Output enable control Operating temperature range (C) -40 to 85 Rating Catalog Output type LVDS Input type LVCMOS, LVDS, LVPECL open-in-new Find other Clock buffers

Package | Pins | Size

VQFN (RGZ) 48 49 mm² 7 x 7 open-in-new Find other Clock buffers

Features

  • Dual 1:8 Differential Buffer
  • Low Additive Jitter <300 fs RMS in
    10 kHz to 20 MHz
  • Low Within Bank Output Skew of 50 ps (Max)
  • Universal Inputs Accept LVDS, LVPECL, LVCMOS
  • One Input Dedicated for Eight Outputs
  • Total of 16 LVDS Outputs, ANSI EIA/TIA-644A
    Standard Compatible
  • Clock Frequency up to 800 MHz
  • 2.375–2.625V Device Power Supply
  • LVDS Reference Voltage, VAC_REF,
    Available for Capacitive Coupled Inputs
  • Industrial Temperature Range –40°C to 85°C
  • Packaged in 7mm × 7mm 48-Pin QFN (RGZ)
  • ESD Protection Exceeds 3 kV HBM, 1 kV CDM
  • APPLICATIONS
    • Telecommunications/Networking
    • Medical Imaging
    • Test and Measurement Equipment
    • Wireless Communications
    • General Purpose Clocking

open-in-new Find other Clock buffers

Description

The CDCLVD2108 clock buffer distributes two clock inputs (IN0, IN1) to a total of 16 pairs of differential LVDS clock outputs (OUT0, OUT15). Each buffer block consists of one input and 8 LVDS outputs. The inputs can either be LVDS, LVPECL, or LVCMOS.

The CDCLVD2108 is specifically designed for driving 50- transmission lines. In case of driving the inputs in single ended mode, the appropriate bias voltage (VAC_REF) should be applied to the unused negative input pin.

Using the control pin (EN) outputs can be either disabled or enabled. If the EN pin is left open all outputs are active, if switched to a logical "0" all outputs are disabled (static logical 0), if switched to a logical "1", OUT (8..15) are switched off and OUT (0..7) are active. The part supports a fail safe function. It incorporates an input hysteresis, which prevents random oscillation of the outputs in absence of an input signal.

The device operates in 2.5V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD2108 is packaged in small 48-pin, 7-mm × 7-mm QFN package.

open-in-new Find other Clock buffers
Download
Similar products you might be interested in
open-in-new Compare products
Similar but not functionally equivalent to the compared device:
LMK00301 ACTIVE 3-GHz, 10-Output Differential Fanout Buffer / Level Translator Ultra low additive jitter,1:10 Universal Differential Buffer that can support LVDS

Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 1
Type Title Date
* Datasheet Dual 1:8 Low Additive Jitter LVDS Buffer datasheet (Rev. C) Dec. 21, 2010

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
149
Description
The CDCLVD1212/CDCLVD2106 are high-performance, low-additive jitter clock buffers. They have two universal input buffers that support single-ended or differential clock inputs and are selectable through a control pin (for CDCLVD1212 only). The devices also feature on-chip bias generators that can (...)
Features
  • Easy-to-use evaluation board to fan out low-phase noise clocks
  • Easy device setup
  • Fast configuration
  • Control pins configurable through jumpers
  • Board powered at 2.5 V
  • Single-ended or differential input clocks
  • Device supports twelve LVDS outputs, EVM supports four LVDS outputs
EVALUATION BOARDS Download
149
Description
The CDCLVD1212/CDCLVD2106 are high-performance, low-additive jitter clock buffers. They have two universal input buffers that support single-ended or differential clock inputs and are selectable through a control pin (for CDCLVD1212 only). The devices also feature on-chip bias generators that can (...)
Features
  • Easy-to-use evaluation board to fan out low-phase noise clocks
  • Easy device setup
  • Fast configuration
  • Control pins configurable through jumpers
  • Board powered at 2.5 V
  • Single-ended or differential input clocks
  • Device supports twelve LVDS outputs, EVM supports four LVDS outputs

Design tools & simulation

SIMULATION MODELS Download
SLLM096B.ZIP (15 KB) - IBIS Model
SIMULATION TOOLS Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)

CAD/CAE symbols

Package Pins Download
VQFN (RGZ) 48 View options

Ordering & quality

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos

Related videos