CDCLVP1204

ACTIVE

Low Jitter, 2-Input Selectable 1:4 Universal-to-LVPECL Buffer

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Product details

Parameters

Function Differential Additive RMS jitter (Typ) (fs) 57 Output frequency (Max) (MHz) 2000 Number of outputs 4 Output supply voltage (V) 2.5, 3.3 Core supply voltage (V) 2.5, 3.3 Output skew (ps) 15 Features 2:4 fanout Operating temperature range (C) -40 to 85 Rating Catalog Output type LVPECL Input type LVCMOS, LVDS, LVPECL open-in-new Find other Clock buffers

Package | Pins | Size

VQFN (RGT) 16 9 mm² 3 x 3 open-in-new Find other Clock buffers

Features

  • 2:4 Differential Buffer
  • Selectable Clock Inputs Through Control Terminal
  • Universal Inputs Accept LVPECL, LVDS, and
    LVCMOS/LVTTL
  • Four LVPECL Outputs
  • Maximum Clock Frequency: 2 GHz
  • Maximum Core Current Consumption: 45 mA
  • Very Low Additive Jitter: <100 fs, RMS in 10-kHz
    to 20-MHz Offset Range:
    • 57 fs, RMS (typical) at 122.88 MHz
    • 48 fs, RMS (typical) at 156.25 MHz
    • 30 fs, RMS (typical) at 312.5 MHz
  • 2.375-V to 3.6-V Device Power Supply
  • Maximum Propagation Delay: 450 ps
  • Maximum Output Skew: 15 ps
  • LVPECL Reference Voltage, VAC_REF, Available
    for Capacitive-Coupled Inputs
  • Industrial Temperature Range: –40°C to +85°C
  • Supports 105°C PCB Temperature (Measured at
    Thermal Pad)
  • ESD Protection Exceeds 2 kV (HBM)
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Description

The CDCLVP1204 is a highly versatile, low additive jitter buffer that can generate four copies of LVPECL clock outputs from one of two selectable LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. The CDCLVP1204 features an on-chip multiplexer (MUX) for selecting one of two inputs that can be easily configured solely through a control terminal. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 15 ps, making the device a perfect choice for use in demanding applications.

The CDCLVP1204 clock buffer distributes one of two selectable clock inputs (IN0, IN1) to four pairs of differential LVPECL clock outputs (OUT0, OUT3) with minimum skew for clock distribution. The CDCLVP1204 can accept two clock sources into an input multiplexer. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.

The CDCLVP1204 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) must be applied to the unused negative input terminal. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.

The CDCLVP1204 is characterized for operation from –40°C to +85°C.

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Similar but not functionally equivalent to the compared device:
LMK00304 ACTIVE 3.1-GHz Differential Clock Buffer/Level Translator Ultra low additive jitter,1:4 Universal Differential Buffer that can support LVPECL

Technical documentation

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Type Title Date
* Datasheet CDCLVP1204 Four LVPECL Output, High-Performance Clock Buffer datasheet (Rev. F) Sep. 03, 2015
User guides CDCLVP1204 User's Guide Jul. 09, 2009

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
149
Description

The CDCLVP1204 is a high-performance, low additive phase noise clock buffer. It has two universal input buffers that support either single-ended or differential clock inputs, selectable through a control pin. The device also features on-chip bias generators that can provide the LVPECL common-mode (...)

Features
  • Easy-to-use evaluation board to fan out low phase noise clocks
  • Easy device setup
  • Fast configuration
  • Control pins configurable through jumpers
  • Board powered at +2.5-/+3.3V
  • Single-ended or differential input clocks
  • CDCLVP1204 supports four LVPECL outputs; CDCLVP1204EVM supports two LVPECL outputs

Design tools & simulation

SIMULATION MODELS Download
SLAM142.ZIP (116 KB) - HSpice Model
SIMULATION MODELS Download
SLLM056B.ZIP (40 KB) - IBIS Model
SIMULATION TOOLS Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)

Reference designs

REFERENCE DESIGNS Download
SDI Video Aggregation Reference Design
TIDA-00352 This verified reference design is a complete four channel SDI aggregation and de-aggregation solution. One TLK10022 is used to aggregate four synchronous HD-SDI sources together into one 5.94 Gbps serial link. The serial data is transferred via copper or optical fiber where a second TLK10022 is used (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
DisplayPort Video 4:1 Aggregation Reference Design
TIDA-00309 This verified reference design is a complete four channel DisplayPort aggregation and de-aggregation solution. One TLK10022 is used to aggregate four synchronous DisplayPort (DP) sources together into one 10.8 Gbps serial link. The serial data is transferred via copper or optical fiber where a (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Gigabit Ethernet Link Aggregator Reference Design
TIDA-00269 The Gigabit Ethernet Link Aggregator reference design features the TLK10081 device which is a multi-rate link aggregator intended for use in high-speed bi-directional point-to-point data transmission systems to reduce the number of physical links by multiplexing lower speed serial links into higher (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Dual-channel XAUI to SFI Reference Design for Systems with Two or More SFP+ Optical Ports
TIDA-00234 The TIDA-00234 XAUI to SFI reference design is intended for Enterprise and Service Provider Networking applications like Ethernet Switches and Routers that implement multiple 10G Ethernet compliant Optical (SFP+) ports. This reference design features the TLK10232 device which is the most compact (...)
document-generic Schematic document-generic User guide

CAD/CAE symbols

Package Pins Download
VQFN (RGT) 16 View options

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