Product details

Function Single-ended Additive RMS jitter (typ) (fs) 70 Output frequency (max) (MHz) 250 Number of outputs 2 Output supply voltage (V) 2.5, 3.3 Core supply voltage (V) 2.5, 3.3 Output skew (ps) 50 Features 1:2 fanout, Output enable control Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVCMOS Input type LVCMOS
Function Single-ended Additive RMS jitter (typ) (fs) 70 Output frequency (max) (MHz) 250 Number of outputs 2 Output supply voltage (V) 2.5, 3.3 Core supply voltage (V) 2.5, 3.3 Output skew (ps) 50 Features 1:2 fanout, Output enable control Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVCMOS Input type LVCMOS
TSSOP (PW) 8 19.2 mm² 3 x 6.4
  • High-Performance 1:2, 1:3, 1:4, 1:6, 1:8, 1:10, 1:12 LVCMOS Clock Buffer Family
  • Very Low Pin-to-Pin Skew < 50 ps
  • Very Low Additive Jitter < 100 fs
  • Supply Voltage: 3.3 V or 2.5 V
  • fmax = 250 MHz for 3.3 V
    fmax = 180 MHz for 2.5 V
  • Operating Temperature Range: –40°C to 85°C
  • Available in 8-, 14-, 16-, 20-, 24-Pin TSSOP Package (All Pin-Compatible)
  • High-Performance 1:2, 1:3, 1:4, 1:6, 1:8, 1:10, 1:12 LVCMOS Clock Buffer Family
  • Very Low Pin-to-Pin Skew < 50 ps
  • Very Low Additive Jitter < 100 fs
  • Supply Voltage: 3.3 V or 2.5 V
  • fmax = 250 MHz for 3.3 V
    fmax = 180 MHz for 2.5 V
  • Operating Temperature Range: –40°C to 85°C
  • Available in 8-, 14-, 16-, 20-, 24-Pin TSSOP Package (All Pin-Compatible)

The CDCLVC11xx is a modular, high-performance, low-skew, general-purpose clock buffer family from Texas Instruments.

The entire family is designed with a modular approach in mind. It is intended to round up TI’s series of LVCMOS clock generators.

Seven different fan-out variations, 1:2 to 1:12, are available. All of the devices are pin-compatible to each other for easy handling.

All family members share the same high performing characteristics such as low additive jitter, low skew, and wide operating temperature range.

The CDCLVC11xx supports an asynchronous output enable control (1G) which switches the outputs into a low state when 1G is low.

The CDCLVC11xx family operates in a 2.5-V and
3.3-V environment and are characterized for operation from –40°C to 85°C.

The CDCLVC11xx is a modular, high-performance, low-skew, general-purpose clock buffer family from Texas Instruments.

The entire family is designed with a modular approach in mind. It is intended to round up TI’s series of LVCMOS clock generators.

Seven different fan-out variations, 1:2 to 1:12, are available. All of the devices are pin-compatible to each other for easy handling.

All family members share the same high performing characteristics such as low additive jitter, low skew, and wide operating temperature range.

The CDCLVC11xx supports an asynchronous output enable control (1G) which switches the outputs into a low state when 1G is low.

The CDCLVC11xx family operates in a 2.5-V and
3.3-V environment and are characterized for operation from –40°C to 85°C.

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LMK1C1102 ACTIVE 2-channel output LVCMOS 1.8-V buffer LMK1C1102 is parametrically superior to the CDCLVC1102, more cost-effective than the CDCLVC1102, and has added features, such as synchronous output enable.

Technical documentation

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Type Title Date
* Data sheet CDCLVC11xx 3.3-V and 2.5-V LVCMOS High-Performance Clock Buffer Family datasheet (Rev. B) PDF | HTML 24 Feb 2017
Application note Sine to Square Wave Conversion Using Clock Buffers PDF | HTML 03 Sep 2024
Application note How to Apply 1.8-V Signals to 3.3-V CDCLVC11xx Fanout Clock Buffer 30 Nov 2010

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

CDCLVC1104EVM — CDCLVC1104 Evaluation Module

The CDCLVC1104 is a high-performance, low-additive phase noise LVCMOS clock buffer. It has one LVCMOS input and four LVCMOS outputs. It also has an enable pin. This evaluation module (EVM) is designed to demonstrate the electrical performance of the CDCLVC1104. However, this EVM can also be used (...)
User guide: PDF
Not available on TI.com
Evaluation board

DLPDLCR4710EVM-G2 — Full HD DLP4710 Chipset Evaluation Module

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User guide: PDF
Simulation model

CDCLVC1102/03/04/06/08/10/12 IBIS Model (Rev. B)

SLLM088B.ZIP (263 KB) - IBIS Model
Design tool

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Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
Design tool

PLLATINUMSIM-SW PLLatinum Sim Tool

PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.

Supported products & hardware

Supported products & hardware

Products
RF PLLs & synthesizers
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Clock network synchronizers
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Hardware development
Evaluation board
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Software
Application software & framework
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IDE, configuration, compiler or debugger
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Support software
LMX9830-SW LMX9830 Application Notes, Software, and Tools LMX9838-SW LMX9838 Application Notes, Software, and Tools
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Package Pins CAD symbols, footprints & 3D models
TSSOP (PW) 8 Ultra Librarian

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Information included:
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