Produktdetails

Sample rate (max) (Msps) 100 Resolution (Bits) 12 Number of input channels 8 Interface type Serial LVDS Analog input BW (MHz) 500 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 640 Architecture Pipeline SNR (dB) 70.6 ENOB (Bits) 11.4 SFDR (dB) 86 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 100 Resolution (Bits) 12 Number of input channels 8 Interface type Serial LVDS Analog input BW (MHz) 500 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 640 Architecture Pipeline SNR (dB) 70.6 ENOB (Bits) 11.4 SFDR (dB) 86 Operating temperature range (°C) -40 to 85 Input buffer No
HTQFP (PFP) 80 196 mm² (14 mm × 14 mm)
  • Maximum Sample Rate: 100 MSPS
  • Designed for Low Power:
    • 80 mW per channel at 100 MSPS
  • SNR: 70.6 dBFS
  • SFDR: 85 dBc at 10 MHz, 100 MSPS
  • Serial LVDS ADC Data Outputs:
    • One- or Two-Wire Serialized LVDS Outputs per Channel
    • One-Wire Interface:
      Up to 80 MSPS Sample Rate
    • Two-Wire Interface:
      Up to 100 MSPS Sample Rate
  • Digital Processing Block:
    • Programmable FIR Decimation Filter and Oversampling to Minimize Harmonic Interference
    • Programmable IIR High-Pass Filter to Minimize DC Offset
    • Programmable Digital Gain: 0 dB to 12 dB
  • Low-Frequency Noise Suppression Mode
  • Programmable Mapping Between ADC Input Channels and LVDS Output Pins
  • Channel Averaging Mode
  • Variety of LVDS Test Patterns to Verify
    Data Capture by FPGA or Receiver
  • Package: 12-mm × 12-mm QFP-80
  • Maximum Sample Rate: 100 MSPS
  • Designed for Low Power:
    • 80 mW per channel at 100 MSPS
  • SNR: 70.6 dBFS
  • SFDR: 85 dBc at 10 MHz, 100 MSPS
  • Serial LVDS ADC Data Outputs:
    • One- or Two-Wire Serialized LVDS Outputs per Channel
    • One-Wire Interface:
      Up to 80 MSPS Sample Rate
    • Two-Wire Interface:
      Up to 100 MSPS Sample Rate
  • Digital Processing Block:
    • Programmable FIR Decimation Filter and Oversampling to Minimize Harmonic Interference
    • Programmable IIR High-Pass Filter to Minimize DC Offset
    • Programmable Digital Gain: 0 dB to 12 dB
  • Low-Frequency Noise Suppression Mode
  • Programmable Mapping Between ADC Input Channels and LVDS Output Pins
  • Channel Averaging Mode
  • Variety of LVDS Test Patterns to Verify
    Data Capture by FPGA or Receiver
  • Package: 12-mm × 12-mm QFP-80

The ADS5295 is a low-power, 12-bit, 100-MSPS, 8-channel analog-to-digital converter (ADC). Low power consumption and integration of multiple channels in a compact package make the device attractive for very high channel count data acquisition systems.

Serial low-voltage differential signaling (LVDS) outputs reduce the number of interface lines and enable high system integration. The ADC digital data can be output over one or two wires of LVDS pins per channel. At high sample rates, the two-wire interface helps keep the serial data rate low, allowing low-cost field-programmable gate array (FPGA)-based receivers to be used.

The device integrates an internal reference trimmed to accurately match across devices. Best performance is expected to be achieved through the internal reference mode. However, the device can be driven with external references as well.

Several digital functions that are commonly used in systems are included in the device. These functions include a low-frequency suppression mode, digital filtering options, and programmable mapping.

For low input frequency applications, the low-frequency noise suppression mode enables noise suppression at low frequencies and improves signal-to-noise ratio (SNR) in the 1-MHz band near dc by approximately 3 dB. Digital filtering options include low-pass, high-pass, and band-pass digital filters, as well as dc offset removal filters. The device also provides programmable mapping of the LVDS output pins and analog input channels. For applications where the 12-bit ADC SNR is not required, the ADS5295 can be configured as an 8-channel, 10-bit ADC with 10x LVDS serialization to reduce the output data rate.

The device is available in a 12-mm × 12-mm QFP-80 package. The ADS5295 is specified over the –40°C to +85°C operating temperature range.

The ADS5295 is a low-power, 12-bit, 100-MSPS, 8-channel analog-to-digital converter (ADC). Low power consumption and integration of multiple channels in a compact package make the device attractive for very high channel count data acquisition systems.

Serial low-voltage differential signaling (LVDS) outputs reduce the number of interface lines and enable high system integration. The ADC digital data can be output over one or two wires of LVDS pins per channel. At high sample rates, the two-wire interface helps keep the serial data rate low, allowing low-cost field-programmable gate array (FPGA)-based receivers to be used.

The device integrates an internal reference trimmed to accurately match across devices. Best performance is expected to be achieved through the internal reference mode. However, the device can be driven with external references as well.

Several digital functions that are commonly used in systems are included in the device. These functions include a low-frequency suppression mode, digital filtering options, and programmable mapping.

For low input frequency applications, the low-frequency noise suppression mode enables noise suppression at low frequencies and improves signal-to-noise ratio (SNR) in the 1-MHz band near dc by approximately 3 dB. Digital filtering options include low-pass, high-pass, and band-pass digital filters, as well as dc offset removal filters. The device also provides programmable mapping of the LVDS output pins and analog input channels. For applications where the 12-bit ADC SNR is not required, the ADS5295 can be configured as an 8-channel, 10-bit ADC with 10x LVDS serialization to reduce the output data rate.

The device is available in a 12-mm × 12-mm QFP-80 package. The ADS5295 is specified over the –40°C to +85°C operating temperature range.

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Technische Dokumentation

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Top-Dokumentation Typ Titel Format-Optionen Neueste englische Version herunterladen Datum
* Datenblatt 12-Bit, 100-MSPS, 8-Channel Analog-to-Digital Converter datasheet 10.12.2012
Anwendungshinweis Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) 22.05.2015
Anwendungshinweis Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) 19.07.2013
Anwendungshinweis Understanding Serial LVDS Capture in High-Speed ADCs 10.07.2013

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