Produktdetails

Number of input channels 2 Resolution (Bits) 12 Sample rate (max) (Msps) 500 Features Decimating Filter, Differential Inputs, High Dynamic Range, Nap Mode, Out of Range Indicator, Power Down Analog input BW (MHz) 1200 Power consumption (typ) (mW) 1600 Operating temperature range (°C) -40 to 85 Rating Catalog
Number of input channels 2 Resolution (Bits) 12 Sample rate (max) (Msps) 500 Features Decimating Filter, Differential Inputs, High Dynamic Range, Nap Mode, Out of Range Indicator, Power Down Analog input BW (MHz) 1200 Power consumption (typ) (mW) 1600 Operating temperature range (°C) -40 to 85 Rating Catalog
NFBGA (ZAY) 196 144 mm² (12 mm × 12 mm)
  • Dual Channel
  • 12-Bit Resolution
  • Maximum Clock Rate: 500 Msps
  • Low Swing Fullscale Input: 1.0 Vpp
  • Analog Input Buffer with High Impedance Input
  • Input Bandwidth (3dB): >1.2GHz
  • Data Output Interface: DDR LVDS
  • 196-Pin BGA Package (12×12mm)
  • Power Dissipation: 800mW/ch
  • Performance at fin = 230 MHz IF
    • SNR: 60.6 dBFS
    • SFDR: 77 dBc
  • Performance at fin = 700 MHz IF
    • SNR: 59.4 dBFS
    • SFDR: 70 dBc
  • Receive Mode: 2x Decimation with Low Pass or
    High Pass Filter
  • Feedback Mode: Burst Mode Output for Full
    Bandwidth DPD Feedback
  • Dual Channel
  • 12-Bit Resolution
  • Maximum Clock Rate: 500 Msps
  • Low Swing Fullscale Input: 1.0 Vpp
  • Analog Input Buffer with High Impedance Input
  • Input Bandwidth (3dB): >1.2GHz
  • Data Output Interface: DDR LVDS
  • 196-Pin BGA Package (12×12mm)
  • Power Dissipation: 800mW/ch
  • Performance at fin = 230 MHz IF
    • SNR: 60.6 dBFS
    • SFDR: 77 dBc
  • Performance at fin = 700 MHz IF
    • SNR: 59.4 dBFS
    • SFDR: 70 dBc
  • Receive Mode: 2x Decimation with Low Pass or
    High Pass Filter
  • Feedback Mode: Burst Mode Output for Full
    Bandwidth DPD Feedback

The ADS54T04 is a high linearity dual channel 12-bit, 500 MSPS analog-to-digital converter (ADC) easing front end filter design for wide bandwidth receivers. The analog input buffer isolates the internal switching of the on-chip track-and-hold from disturbing the signal source as well as providing a high-impedance input. Two output modes are available for the output data – it can be decimated by two or the data can be output in burst mode. The burst mode output is designed specifically for DPD feedback applications where high resolution output data is available for a short period of time. Designed for high SFDR, the ADC has low-noise performance and outstanding spurious-free dynamic range over a large input-frequency range. The device is available in a 196pin BGA package and is specified over the full industrial temperature range (–40°C to 85°C).

The ADS54T04 is a high linearity dual channel 12-bit, 500 MSPS analog-to-digital converter (ADC) easing front end filter design for wide bandwidth receivers. The analog input buffer isolates the internal switching of the on-chip track-and-hold from disturbing the signal source as well as providing a high-impedance input. Two output modes are available for the output data – it can be decimated by two or the data can be output in burst mode. The burst mode output is designed specifically for DPD feedback applications where high resolution output data is available for a short period of time. Designed for high SFDR, the ADC has low-noise performance and outstanding spurious-free dynamic range over a large input-frequency range. The device is available in a 196pin BGA package and is specified over the full industrial temperature range (–40°C to 85°C).

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Technische Dokumentation

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Top-Dokumentation Typ Titel Format-Optionen Neueste englische Version herunterladen Datum
* Datenblatt Dual Channel 12-Bit 500Msps Receiver and Feedback IC datasheet (Rev. B) 08.01.2014
Anwendungshinweis Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) 22.05.2015
Anwendungshinweis Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) 19.07.2013

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