Produktdetails

Number of channels 1 Vs (max) (V) 36 Vs (min) (V) 4.5 Input offset (±) (max) (µV) 50 Voltage gain (min) (V/V) 1 Voltage gain (max) (V/V) 10000 Noise at 1 kHz (typ) (nV√Hz) 11 Features Overvoltage protection CMRR (min) (dB) 115 Input offset drift (±) (max) (µV/°C) 0.25 Input bias current (±) (max) (nA) 2 Iq (typ) (mA) 2.2 Bandwidth at min gain (typ) (MHz) 1 Gain error (±) (max) (%) 0.5 Operating temperature range (°C) -40 to 85 Rating Catalog Type Resistor Gain nonlinearity (±) (max) (%) 0.002 Output swing headroom (to negative supply) (typ) (V) 1.3 Output swing headroom (to positive supply) (typ) (V) -1.3 Input common mode headroom (to negative supply) (typ) (V) 1.5 Input common mode headroom (to positive supply) (typ) (V) -1.5 Noise at 0.1 Hz to 10 Hz (typ) (µVPP) 0.4
Number of channels 1 Vs (max) (V) 36 Vs (min) (V) 4.5 Input offset (±) (max) (µV) 50 Voltage gain (min) (V/V) 1 Voltage gain (max) (V/V) 10000 Noise at 1 kHz (typ) (nV√Hz) 11 Features Overvoltage protection CMRR (min) (dB) 115 Input offset drift (±) (max) (µV/°C) 0.25 Input bias current (±) (max) (nA) 2 Iq (typ) (mA) 2.2 Bandwidth at min gain (typ) (MHz) 1 Gain error (±) (max) (%) 0.5 Operating temperature range (°C) -40 to 85 Rating Catalog Type Resistor Gain nonlinearity (±) (max) (%) 0.002 Output swing headroom (to negative supply) (typ) (V) 1.3 Output swing headroom (to positive supply) (typ) (V) -1.3 Input common mode headroom (to negative supply) (typ) (V) 1.5 Input common mode headroom (to positive supply) (typ) (V) -1.5 Noise at 0.1 Hz to 10 Hz (typ) (µVPP) 0.4
PDIP (P) 8 92.5083 mm² 9.81 x 9.43 SOIC (DW) 16 106.09 mm² 10.3 x 10.3
  • Low offset voltage: 50µV maximum for high gains
  • Low drift: 0.3µV/°C maximum for high gains
  • Low input bias current: 2nA maximum
  • High common-mode rejection: 115dB minimum
  • Input over-voltage protection: ±40V
  • Wide supply range: ±2.25V to ±18V
  • Packages: PDIP-8 and SOIC-16
  • Low offset voltage: 50µV maximum for high gains
  • Low drift: 0.3µV/°C maximum for high gains
  • Low input bias current: 2nA maximum
  • High common-mode rejection: 115dB minimum
  • Input over-voltage protection: ±40V
  • Wide supply range: ±2.25V to ±18V
  • Packages: PDIP-8 and SOIC-16

The INA114 is a low-cost, general-purpose instrumentation amplifier offering excellent accuracy. The versatile three-op-amp design and small size make this device an excellent choice for a wide range of applications.

A single external resistor sets any gain from 1 to 10,000. Internal input protection withstands up to ±40V without damage.

The INA114 is laser trimmed for very low offset voltage (50µV), low drift (0.3µV/°C), and high common-mode rejection (115dB at G = 1000). The device operates with power supplies as low as ±2.25V, allowing use in battery-operated and single 5V supply systems.

The INA114 is available in 8-pin PDIP and 16-pin SOIC surface-mount packages. Both are specified for a temperature range of −40°C to +85°C.

The INA114 is a low-cost, general-purpose instrumentation amplifier offering excellent accuracy. The versatile three-op-amp design and small size make this device an excellent choice for a wide range of applications.

A single external resistor sets any gain from 1 to 10,000. Internal input protection withstands up to ±40V without damage.

The INA114 is laser trimmed for very low offset voltage (50µV), low drift (0.3µV/°C), and high common-mode rejection (115dB at G = 1000). The device operates with power supplies as low as ±2.25V, allowing use in battery-operated and single 5V supply systems.

The INA114 is available in 8-pin PDIP and 16-pin SOIC surface-mount packages. Both are specified for a temperature range of −40°C to +85°C.

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Technische Dokumentation

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Top-Dokumentation Typ Titel Format-Optionen Datum
* Data sheet INA114 Precision Instrumentation Amplifier datasheet (Rev. B) PDF | HTML 23 Jan 2026
Application note Importance of Input Bias Current Return Paths in Instrumentation Amplifier Apps PDF | HTML 27 Jul 2021
E-book The Signal e-book: A compendium of blog posts on op amp design topics 28 Mär 2017
Application note Use Low-Impedance Bridges on 4-20mA Current Loop 27 Sep 2000

Design und Entwicklung

Weitere Bedingungen oder erforderliche Ressourcen enthält gegebenenfalls die Detailseite, die Sie durch Klicken auf einen der unten stehenden Titel erreichen.

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INA114 PSpice Model (Rev. B)

SBOM013B.ZIP (61 KB) - PSpice Model
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INA114 Reference Project (PSpice) (Rev. A)

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INA114 TINA-TI Reference Design (Rev. C)

SBOC138C.TSC (93 KB) - TINA-TI Reference Design
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INA114 TINA-TI Spice Model (Rev. A)

SBOM207A.ZIP (4 KB) - TINA-TI Spice Model
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Benutzerhandbuch: PDF
Gehäuse Pins CAD-Symbole, Footprints und 3D-Modelle
PDIP (P) 8 Ultra Librarian
SOIC (DW) 16 Ultra Librarian

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