ADS6142 14-Bit, 65-MSPS Analog-to-Digital Converter (ADC) | TI.com

ADS6142
This product has been released to the market and is available for purchase. For some products, newer alternatives may be available.
14-Bit, 65-MSPS Analog-to-Digital Converter (ADC)

 

Recommended alternative parts

  • ADS4142  -  65MSPS with 67% power reduction

Description

ADS6145/ADS6144/ADS6143/ADS6142 (ADS614X) are a family of 14-bit A/D converters with sampling frequencies up to 125 MSPS. The high performance and low power consumption of the ADS614X are combined in a compact 32 QFN package. An internal high bandwidth sample and hold and a low jitter clock buffer help to achieve high SNR and high SFDR even at high input frequencies.

The ADS614X feature coarse and fine gain options to improve SFDR performance at lower full-scale analog input ranges.

The digital data outputs are either parallel CMOS or DDR (Double Data Rate) LVDS. Several features exist to ease data capture such as — controls for output clock position and output buffer drive strength, LVDS current, and internal termination programmability.

The output interface type, gain, and other functions are programmed using a 3-wire serial interface. Alternatively, some functions are configured using dedicated parallel pins so the device powers up to the desired state.

The ADS614X include internal references while eliminating traditional reference pins and associated external decoupling. External reference mode is also supported.

The ADS614X are specified over the industrial temperature range (-40°C to 85°C).

Features

  • Maximum Sample Rate: 125 MSPS
  • 14-Bit Resolution with No Missing Codes
  • 3.5 dB Coarse Gain and up to 6 dB Programmable Fine Gain for SNR/SFDR Trade-Off
  • Parallel CMOS and Double Data Rate (DDR) LVDS Output Options
  • Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs, and Clock Amplitude Down to 400 mVPP
  • Clock Duty Cycle Stabilizer
  • Internal Reference with Support for External Reference
  • No External Decoupling Required for References
  • Programmable Output Clock Position and Drive Strength to Ease Data Capture
  • 3.3-V Analog and 1.8-V to 3.3-V Digital Supply
  • 32-QFN Package (5 mm × 5 mm)
  • Pin Compatible 12-Bit Family (ADS612X)
  • APPLICATIONS
    • Wireless Communications Infrastructure
    • Software Defined Radio
    • Power Amplifier Linearization
    • 802.16d/e
    • Test and Measurement Instrumentation
    • High Definition Video
    • Medical Imaging
    • Radar Systems

Parametrics

Compare all products in High-speed ADCs (>10MSPS) Email Download to Excel
Part number Order Sample rate (Max) (MSPS) Features Resolution (Bits) Number of input channels SNR (dB) ENOB (Bits) SFDR (dB) Power consumption (Typ) (mW) Input range (Vp-p) Interface Operating temperature range (C) Analog input BW (MHz) Input buffer Package Group Package size: mm2:W x L (PKG) Rating Architecture
ADS6142 Order now 65     Low Power     14     1     74.7     1     95     285     2     DDR LVDS
Parallel CMOS    
-40 to 85     500     No     VQFN | 32     32VQFN: 25 mm2: 5 x 5 (VQFN | 32)     Catalog     Pipeline    
ADS6122 Samples not available 65     Low Power     12     1     71.8     11.56     95     285     2     DDR LVDS
Parallel CMOS    
-40 to 85     500     No     VQFN | 32     32VQFN: 25 mm2: 5 x 5 (VQFN | 32)     Catalog     Pipeline    
ADS6123 Samples not available 80     Low Power     12     1     71.8     11.55     93     318     2     DDR LVDS
Parallel CMOS    
-40 to 85     500     No     VQFN | 32     32VQFN: 25 mm2: 5 x 5 (VQFN | 32)     Catalog     Pipeline    
ADS6124 Samples not available 105     Low Power     12     1     71.5     11.5     91     374     2     DDR LVDS
Parallel CMOS    
-40 to 85     500     No     VQFN | 32     32VQFN: 25 mm2: 5 x 5 (VQFN | 32)     Catalog     Pipeline    
ADS6125 Samples not available 125     Low Power     12     1     71.5     11.4     90     417     2     DDR LVDS
Parallel CMOS