Product details

Sample rate (Max) (MSPS) 190 Resolution (Bits) 14 Number of input channels 1 Interface type Parallel CMOS, Parallel LVDS Analog input BW (MHz) 500 Features High Performance Rating Catalog Input range (Vp-p) 2 Power consumption (Typ) (mW) 1130 Architecture Pipeline SNR (dB) 73.8 ENOB (Bits) 11.8 SFDR (dB) 90 Operating temperature range (C) -40 to 85 Input buffer No
Sample rate (Max) (MSPS) 190 Resolution (Bits) 14 Number of input channels 1 Interface type Parallel CMOS, Parallel LVDS Analog input BW (MHz) 500 Features High Performance Rating Catalog Input range (Vp-p) 2 Power consumption (Typ) (mW) 1130 Architecture Pipeline SNR (dB) 73.8 ENOB (Bits) 11.8 SFDR (dB) 90 Operating temperature range (C) -40 to 85 Input buffer No
VQFN (RGZ) 48 49 mm² 7.0 x 7.0
  • Maximum Sample Rate: 190 MSPS
  • 14-Bit Resolution
  • No Missing Codes
  • Total Power Dissipation 1.1 W
  • Internal Sample and Hold
  • 73.2-dBFS SNR at 70-MHz IF
  • 87-dBc SFDR at 70-MHz IF, 0 dB gain
  • Double Data Rate (DDR) LVDS and Parallel CMOS Output Options
  • Programmable Gain up to 6 dB for SNR/SFDR Trade-Off at High IF
  • Reduced Power Modes at Lower Sample Rates
  • Supports input clock amplitude down to 400 mVPP
  • Clock Duty Cycle Stabilizer
  • No External Reference Decoupling Required
  • Internal and External Reference Support
  • Programmable Output Clock position to ease data capture
  • 3.3-V Analog and Digital Supply
  • 48-QFN Package (7 mm × 7 mm)
  • APPLICATIONS
    • Wireless Communications Infrastructure
    • Software Defined Radio
    • Power Amplifier Linearization
    • 802.16d/e
    • Test and Measurement Instrumentation
    • High Definition Video
    • Medical Imaging
    • Radar Systems

  • Maximum Sample Rate: 190 MSPS
  • 14-Bit Resolution
  • No Missing Codes
  • Total Power Dissipation 1.1 W
  • Internal Sample and Hold
  • 73.2-dBFS SNR at 70-MHz IF
  • 87-dBc SFDR at 70-MHz IF, 0 dB gain
  • Double Data Rate (DDR) LVDS and Parallel CMOS Output Options
  • Programmable Gain up to 6 dB for SNR/SFDR Trade-Off at High IF
  • Reduced Power Modes at Lower Sample Rates
  • Supports input clock amplitude down to 400 mVPP
  • Clock Duty Cycle Stabilizer
  • No External Reference Decoupling Required
  • Internal and External Reference Support
  • Programmable Output Clock position to ease data capture
  • 3.3-V Analog and Digital Supply
  • 48-QFN Package (7 mm × 7 mm)
  • APPLICATIONS
    • Wireless Communications Infrastructure
    • Software Defined Radio
    • Power Amplifier Linearization
    • 802.16d/e
    • Test and Measurement Instrumentation
    • High Definition Video
    • Medical Imaging
    • Radar Systems

ADS5546 is a high performance 14-bit, 190-MSPS A/D converter. It offers state-of-the art functionality and performance using advanced techniques to minimize board space. Using an internal sample and hold and low jitter clock buffer, the ADC supports both high SNR and high SFDR at high input frequencies. It features programmable gain options that can be used to improve SFDR performance at lower full-scale analog input ranges.

In a compact 48-pin QFN, the device offers fully differential LVDS DDR (Double Data Rate) interface while parallel CMOS outputs can also be selected. Flexible output clock position programmability is available to ease capture and trade-off setup for hold times. At lower sampling rates, the ADC can be operated at scaled down power with no loss in performance. ADS5546 includes an internal reference, while eliminating the traditional reference pins and associated external decoupling. The device also supports an external reference mode.

The device is specified over the industrial temperature range (-40°C to 85°C).

ADS5546 is a high performance 14-bit, 190-MSPS A/D converter. It offers state-of-the art functionality and performance using advanced techniques to minimize board space. Using an internal sample and hold and low jitter clock buffer, the ADC supports both high SNR and high SFDR at high input frequencies. It features programmable gain options that can be used to improve SFDR performance at lower full-scale analog input ranges.

In a compact 48-pin QFN, the device offers fully differential LVDS DDR (Double Data Rate) interface while parallel CMOS outputs can also be selected. Flexible output clock position programmability is available to ease capture and trade-off setup for hold times. At lower sampling rates, the ADC can be operated at scaled down power with no loss in performance. ADS5546 includes an internal reference, while eliminating the traditional reference pins and associated external decoupling. The device also supports an external reference mode.

The device is specified over the industrial temperature range (-40°C to 85°C).

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Technical documentation

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Type Title Date
* Data sheet 14-Bits 190 MSPS ADC With DDR LVDS/CMOS Outputs datasheet (Rev. D) 07 May 2007
Technical article Keys to quick success using high-speed data converters 13 Oct 2020
Technical article How to achieve fast frequency hopping 03 Mar 2019
Technical article RF sampling: Learning more about latency 09 Feb 2017
Technical article Why phase noise matters in RF sampling converters 28 Nov 2016
Application note Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) 22 May 2015
Application note Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) 19 Jul 2013
Application note Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) 10 Sep 2010
User guide ADS61x9/55xxEVM User's Guide (Rev B of the EVM board) (Rev. A) 11 Jun 2009
Application note Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio 28 Apr 2009
Application note CDCE62005 as Clock Solution for High-Speed ADCs 04 Sep 2008
Application note CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters 08 Jun 2008
Application note Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 02 Jun 2008
User guide ADS5517/25/27/45/46/47 EVM User's Guide (Rev. C) 03 Jan 2008
Application note QFN Layout Guidelines 28 Jul 2006

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Software programming tool

HSADC-SPI-UTILITY — High Speed ADC SPI Programming Tool

Support software

DATACONVERTERPRO-SW — High-speed data converter pro software

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter and analog front-end (AFE) platforms. Designed to support the entire TSW14xxx series of data-capture and pattern-generation cards (...)
Simulation model

ADS5545/46/47/25/27 IBIS Model

SLWM001.ZIP (240 KB) - IBIS Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Calculation tool

JITTER-SNR-CALC — Jitter and SNR Calculator for ADCs

JITTER-SNR-CALC can be used for calculating theoretical Signal to Noise (SNR) performance of ADCs based on input frequency and clock jitter.
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VQFN (RGZ) 48 View options

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