ADC3221

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Dual-Channel, 12-Bit, 25-MSPS Analog-to-Digital Converter (ADC)

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Product details

Parameters

Sample rate (Max) (MSPS) 25 Resolution (Bits) 12 Number of input channels 2 Interface Serial LVDS Analog input BW (MHz) 540 Features Low Power Rating Catalog Input range (Vp-p) 2 Power consumption (Typ) (mW) 120 Architecture Pipeline SNR (dB) 71.2 ENOB (Bits) 11.5 SFDR (dB) 96 Operating temperature range (C) -40 to 85 Input buffer No open-in-new Find other High-speed ADCs (>10MSPS)

Package | Pins | Size

VQFN (RGZ) 48 49 mm² 7 x 7 open-in-new Find other High-speed ADCs (>10MSPS)

Features

  • Dual channel
  • 12-Bit resolution
  • Single supply: 1.8 V
  • Serial LVDS interface (SLVDS)
  • Flexible input clock buffer with divide-by-1, -2, -4
  • SNR = 70.2 dBFS, SFDR = 87 dBc at
    fIN = 70 MHz
  • Ultra-low power consumption:
    • 116 mW/Ch at 125 MSPS
  • Channel isolation: 105 dB
  • Internal dither and chopper
  • Support for multi-chip synchronization
  • Pin-to-pin compatible with 14-Bit version
  • Package: VQFN-48 (7 mm × 7 mm)

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open-in-new Find other High-speed ADCs (>10MSPS)

Description

The ADC322x are a high-linearity, ultra-low power, dual-channel, 12-bit, 25-MSPS to 125-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock architecture design and the SYSREF input enables complete system synchronization. The ADC322x family supports serial low-voltage differential signaling (LVDS) in order to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where each ADC data are serialized and output over two LVDS pairs. Optionally, a one-wire serial LVDS interface is available. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 12-bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.

open-in-new Find other High-speed ADCs (>10MSPS)
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Technical documentation

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Type Title Date
* Datasheet ADC322x Dual-Channel, 12-Bit, 25-MSPS to 125-MSPS, Analog-to-Digital Converters datasheet (Rev. D) Sep. 19, 2019
User guides ADC3xxxEVM and ADC3xJxxEVM User's Guide (Rev. D) Aug. 24, 2018

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
Description

The ADC3221 EVM demonstrates the performance of a low power dual 25Msps 12 bit ADC. It includes the ADC3221 device and TI voltage regulators to provide the necessary voltages. The input for the ADC is by default connected to the transformer input which can be connected to a 50 ohm single ended (...)

Features
  • Single 1.8V supply simplify power requirements
  • Serial LVDS interface simplify digital interface and layout requirements
  • On chip Dither to improve SFDR
  • On chip Chopper to improve 1/f noise
  • Input clock buffer with 1/2/4 divider to simplify clocking
  • Pin compatibility between 12 and 14 bit versions
  • Supports (...)

Design tools & simulation

SIMULATION MODELS Download
SLAM241.ZIP (31 KB) - IBIS Model
GERBER FILES Download
SBAC207.ZIP (6373 KB)

CAD/CAE symbols

Package Pins Download
VQFN (RGZ) 48 View options

Ordering & quality

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