Product details

Sample rate (Max) (MSPS) 125 Resolution (Bits) 11 Number of input channels 2 Interface type Serial LVDS Analog input BW (MHz) 450 Features High Performance Rating Catalog Input range (Vp-p) 2 Power consumption (Typ) (mW) 740 Architecture Pipeline SNR (dB) 67.2 ENOB (Bits) 10.8 SFDR (dB) 89 Operating temperature range (C) -40 to 85 Input buffer No
Sample rate (Max) (MSPS) 125 Resolution (Bits) 11 Number of input channels 2 Interface type Serial LVDS Analog input BW (MHz) 450 Features High Performance Rating Catalog Input range (Vp-p) 2 Power consumption (Typ) (mW) 740 Architecture Pipeline SNR (dB) 67.2 ENOB (Bits) 10.8 SFDR (dB) 89 Operating temperature range (C) -40 to 85 Input buffer No
VQFN (RGC) 64 81 mm² 9 x 9 VQFN (RGC) 64
  • Maximum Sample Rate: 125 MSPS
  • 11-Bit Resolution With No Missing Codes
  • 82 dBc SFDR at Fin = 117 MHz
  • 67 dBFS SNR at Fin = 117 MHz
  • 77.5 dBFS SNR at Fin = 117 MHz, 20MHz bandwidth
    using technology
  • 92 dB Crosstalk
  • Parallel CMOS and DDR LVDS Output Options
  • 3.5 dB Coarse Gain and Programmable Fine Gain
    up to 6 dB for SNR/SFDR Trade-Off
  • Digital Processing Block With:
    • Offset Correction
    • Fine Gain Correction, in Steps of 0.05 dB
    • Decimation by 2/4/8
    • Built-in and Custom Programmable 24-Tap Low/High/
      Band Pass Filters
  • Supports Sine, LVPECL, LVDS and LVCMOS Clocks and
    Amplitude Down to 400 mVPP
  • Clock Duty Cycle Stabilizer
  • Internal Reference; Also Supports External Reference
  • 64-QFN Package (9mm × 9mm)
  • Maximum Sample Rate: 125 MSPS
  • 11-Bit Resolution With No Missing Codes
  • 82 dBc SFDR at Fin = 117 MHz
  • 67 dBFS SNR at Fin = 117 MHz
  • 77.5 dBFS SNR at Fin = 117 MHz, 20MHz bandwidth
    using technology
  • 92 dB Crosstalk
  • Parallel CMOS and DDR LVDS Output Options
  • 3.5 dB Coarse Gain and Programmable Fine Gain
    up to 6 dB for SNR/SFDR Trade-Off
  • Digital Processing Block With:
    • Offset Correction
    • Fine Gain Correction, in Steps of 0.05 dB
    • Decimation by 2/4/8
    • Built-in and Custom Programmable 24-Tap Low/High/
      Band Pass Filters
  • Supports Sine, LVPECL, LVDS and LVCMOS Clocks and
    Amplitude Down to 400 mVPP
  • Clock Duty Cycle Stabilizer
  • Internal Reference; Also Supports External Reference
  • 64-QFN Package (9mm × 9mm)

ADS62C15 is a dual channel 11-bit A/D converter with maximum sample rates up to 125 MSPS. It combines high performance and low power consumption in a compact 64 QFN package. Using an internal sample and hold and low jitter clock buffer, the ADC supports high SNR and high SFDR at high input frequencies. It has coarse and fine gain options that can be used to improve SFDR performance at lower full-scale input ranges.

ADS62C15 uses proprietary technology that can be used to overcome SNR limitation due to quantization noise (for bandwidths less than Nyquist, Fs/2). It includes a digital processing block that consists of several useful and commonly used digital functions such as ADC offset correction, fine gain correction (in steps of 0.05 dB), decimation by 2,4,8 and in-built and custom programmable filters. By default, the digital processing block is bypassed, and its functions are disabled.

Two output interface options exist – parallel CMOS and DDR LVDS (Double Data Rate). ADS62C15 includes internal references while traditional reference pins and associated decoupling capacitors have been eliminated. The device can also be driven with an external reference. The device is specified over the industrial temperature range (–40°C to 85°C).

ADS62C15 is a dual channel 11-bit A/D converter with maximum sample rates up to 125 MSPS. It combines high performance and low power consumption in a compact 64 QFN package. Using an internal sample and hold and low jitter clock buffer, the ADC supports high SNR and high SFDR at high input frequencies. It has coarse and fine gain options that can be used to improve SFDR performance at lower full-scale input ranges.

ADS62C15 uses proprietary technology that can be used to overcome SNR limitation due to quantization noise (for bandwidths less than Nyquist, Fs/2). It includes a digital processing block that consists of several useful and commonly used digital functions such as ADC offset correction, fine gain correction (in steps of 0.05 dB), decimation by 2,4,8 and in-built and custom programmable filters. By default, the digital processing block is bypassed, and its functions are disabled.

Two output interface options exist – parallel CMOS and DDR LVDS (Double Data Rate). ADS62C15 includes internal references while traditional reference pins and associated decoupling capacitors have been eliminated. The device can also be driven with an external reference. The device is specified over the industrial temperature range (–40°C to 85°C).

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Technical documentation

Design & development

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Software programming tool

HSADC-SPI-UTILITY — High Speed ADC SPI Programming Tool

Support software

DATACONVERTERPRO-SW — High-speed data converter pro software

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter and analog front-end (AFE) platforms. Designed to support the entire TSW14xxx series of data-capture and pattern-generation cards, (...)
Support software

TIGAR Support Files

SBAC120.ZIP (262219 KB)
Simulation model

ADS62Pxx Family TINA-TI Transient Spice Model ADS62Pxx Family TINA-TI Transient Spice Model

Simulation model

ADS62Pxx Family TINA-TI Transient Reference Design ADS62Pxx Family TINA-TI Transient Reference Design

Simulation model

ADS62Pxx IBIS Model (Rev. A) ADS62Pxx IBIS Model (Rev. A)

Simulation tool

PSPICE-FOR-TI PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Design tool

TIGAR (Texas Instruments Graphical Evaluation of ADC Response Tool) (Rev. B) TIGAR (Texas Instruments Graphical Evaluation of ADC Response Tool) (Rev. B)

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VQFN (RGC) 64 View options

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