Quad-Channel, 12-Bit, 125-MSPS Analog-to-Digital Converter (ADC)
Product details
Parameters
Package | Pins | Size
Features
- Maximum Sample Rate: 125 MSPS
- 12-Bit Resolution with No Missing Codes
- 1.65-W Total Power
- Simultaneous Sample and Hold
- 70.3 dBFS SNR at Fin = 50 MHz
- 83 dBc SFDR at Fin = 50 MHz, 0 dB Gain
- 79 dBc SFDR at Fin = 170 MHz, 3.5 dB Gain
- 3.5 dB Coarse Gain and up to 6 dB Programmable Fine Gain for SFDR/SNR Trade-Off
- Serialized LVDS Outputs with Programmable Internal Termination Option
- Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs and Amplitude Down to 400 mVpp Differential
- Internal Reference with External Reference Support
- No External Decoupling Required for References
- 3.3-V Analog and Digital Supply
- 64 QFN Package (9 mm × 9 mm)
- Pin Compatible 14-Bit Family (ADS644X - SLAS532)
- APPLICATIONS
- Base-Station IF Receivers
- Diversity Receivers
- Medical Imaging
- Test Equipment
Description
The ADS6425 is a high performance 12-bit, 125-MSPS quad channel ADC. Serial LVDS data outputs reduce the number of interface lines, resulting in a compact 64-pin QFN package (9 mm × 9 mm) that allows for high system integration density. The device includes a 3.5 dB coarse gain option that can be used to improve SFDR performance with little degradation in SNR. In addition to the coarse gain, fine gain options also exist, programmable in 1dB steps up to 6dB.
The output interface is 2-wire, where each ADC's data is serialized and output over two LVDS pairs. This makes it possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1Gbps easing receiver design. The ADS6425 also includes the traditional 1-wire interface that can be used at lower sampling frequencies.
An internal phase locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock. The bit clock is used to serialize the 12-bit data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs. The LVDS output buffers have features such as programmable LVDS currents, current doubling modes, and internal termination options. These can be used to widen eye-openings and improve signal integrity, easing capture by the receiver.
The ADC channel outputs can be transmitted either as MSB or LSB first and 2s complement or straight binary.
The ADS6425 has internal references, but can also support an external reference mode. The device is specified over the industrial temperature range (-40°C to 85°C).
Technical documentation
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
Description
The ADS6425EVM is a circuit board that allows designers to evaluate the performance of Texas Instruments‘ ADS6425 device, a quad channel 12-bit 125 MSPS analog to digital converter. The ADC features a configurable serialized LVDS outputs which can be directly deserialized using TI‘s (...)
Features
- Transformer coupled analog input path
- Transformer coupled clock input path
- Amplifier path based on the THS4509
- Configurable serialized output modes
- Direct connection to High Speed ADC LVDS System (Deserializer)
- Separate analog and digital supply connections
- www.latticesemi.com/ads6000evminterface
Description
The TSW1405EVM is a low cost data capture circuit board used to evaluate some of Texas Instrumentsâ (TI) most popular high speed analog-to-digital converters (ADC).
ÂThe TSW1405EVM supports a high speed LVDS bus capable of providing 16-bit samples at 1.0 GSPS. The platform supports a 64k sample depth (...)
Features
Software development
Features
- Compatible with TSW1400, TSW1405, TSW1406 and TSW14J10, TSW14J50, TSW14J56, and TSW14J57 pattern-generation and data-capture platforms
- Works with all TI high-speed DAC, ADC, and AFE products
- Provides time-domain and frequency-domain analysis
- Supports single-tone, multi-tone, and modulated (...)
Design tools & simulation
Features
- Leverages Cadence PSpice Technology
- Preinstalled library with a suite of digital models to enable worst-case timing analysis
- Dynamic updates ensure you have access to most current device models
- Optimized for simulation speed without loss of accuracy
- Supports simultaneous analysis of multiple products
- (...)
The ADC Harmonic Calculation tool is an excel based calculator for determining the location in frequency space of high order harmonics following Nyquist aliasing in an analog to digital converter.
Given an ADC sample rate and the span of a signal of interest the calcultor will determine if the 2nd (...)
CAD/CAE symbols
Package | Pins | Download |
---|---|---|
VQFN (RGC) | 64 | View options |
Ordering & quality
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
Recommended products may have parameters, evaluation modules or reference designs related to this TI product.
Support & training
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