DAC5681

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16-Bit, 1.0-GSPS Digital-to-Analog Converter (DAC)

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Product details

Parameters

Resolution (Bits) 16 DAC channels 1 Interface Parallel LVDS Sample/update rate (MSPS) 1000 Features Ultra High Speed Rating Catalog Interpolation 1x Power consumption (Typ) (mW) 650 SFDR (dB) 81 Architecture Current Sink Operating temperature range (C) -40 to 85 Reference: type Int open-in-new Find other High-speed DACs (>10MSPS)

Package | Pins | Size

VQFN (RGC) 64 81 mm² 9 x 9 open-in-new Find other High-speed DACs (>10MSPS)

Features

  • 16-Bit Digital-to-Analog Converter (DAC)
  • 1.0 GSPS Update Rate
  • 16-Bit Wideband Input LVDS Data Bus
    • 8 Sample Input FIFO
    • On-Chip Delay Lock Loop
  • High Performance
    • 73 dBc ACLR WCDMA TM1 at 180 MHz
  • On Chip 1.2 V Reference
  • Differential Scalable Output: 2 to 20 mA
  • Package: 64-Pin 9 × 9 mm QFN
open-in-new Find other High-speed DACs (>10MSPS)

Description

The DAC5681 is a 16-bit 1.0 GSPS digital-to-analog converter (DAC) with wideband LVDS data input and internal voltage reference. The DAC5681 offers superior linearity and noise performance.

The DAC5681 integrates a wideband LVDS port with on-chip termination, providing full 1.0 GSPS data transfer into the DAC and lower EMI than traditional CMOS data interfaces. An on-chip delay lock loop (DLL) simplifies LVDS interfacing by providing skew control for the LVDS input data clock.

The current-steering architecture of the DAC5681 consists of a segmented array of current sinking switches directing up to 20mA of full-scale current to complementary output nodes. An accurate on-chip voltage reference is temperature-compensated and delivers a stable 1.2-V reference voltage. Optionally, an external reference may be used.

The DAC5681 is characterized for operation over the industrial temperature range of –40°C to 85°C and is available in a 64-pin QFN package. The device is pin upgradeable to the other members of the family: the DAC5681Z and DAC5682Z. The single-channel DAC5681Z and dual-channel DAC5682Z both provide optional 2x/4x interpolation and a clock multiplying PLL.

open-in-new Find other High-speed DACs (>10MSPS)
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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 14
Type Title Date
* Datasheet 16-bit 1.0 GSPS Digital-To-Analog Converter (DAC) . datasheet (Rev. C) Aug. 06, 2012
Technical articles Keys to quick success using high-speed data converters Oct. 13, 2020
Application note Q3 2009 Issue Analog Applications Journal Sep. 24, 2018
Technical articles Digital signal processing in RF sampling DACs – part 2 Apr. 04, 2017
Technical articles Digital signal processing in RF sampling DACs - part 1 Feb. 13, 2017
Technical articles Why phase noise matters in RF sampling converters Nov. 28, 2016
Application note High Speed, Digital-to-Analog Converters Basics (Rev. A) Oct. 23, 2012
User guide TSW1400 Pattern Generators May 03, 2012
More literature TI and Altera Ease Design Process with Compatible Evaluation Tools Apr. 25, 2011
More literature TI and Xilinx Ease Design Process with Compatible Evaluation Tools Apr. 25, 2011
Application note Interfacing op amps to high-speed DACs, Part 1: Current-sinking DACs Jul. 14, 2009
Application note Passive Terminations for Current Output DACs Nov. 10, 2008
Application note CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters Jun. 08, 2008
Application note Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 Jun. 02, 2008

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
document-generic User guide
499
Description
The DAC5681EVM is a circuit board that allows designers to evaluate the performance of Texas Instruments' single-channel 16-bit 1.0 GSPS digital-to-analog converter (DAC) featuring a fll 1GSPS DDR LVDS interface. The EVM provides a flexible environment to test the DAC5681 under a variety of clock (...)
Features
Comprehensive test capability for DAC5681 Direct connection to TSW3100 signal generator EVM Programmable Low Jitter Clock Synthesizer capable of working with a VCXO or an external clock source Clock synchronization with TSW3100 for signal integrity Software support with a fully featured GUI for easy (...)
INTERFACE ADAPTER Download
49
Description
The FMC-DAC-Adapter passive interconnect board enables the output of TI’s LVDS input high speed DACs to be directly connected to a standard FMC interconnect header, a typical input on the latest Xilinx FPGA EVMs. This enables users of TI’s high speed DAC EVMs to directly interface to Xilinx (...)
Features
  • Enables direct connection to TI high speed DAC EVM LVDS inputs from the FMC standard header

Software development

SUPPORT SOFTWARE Download
High-speed data converter pro software
DATACONVERTERPRO-SW This high-speed data converter pro GUI is a PC (Windows® XP/7 compatible) program designed to aid in evaluation of most TI high-speed data converter and analog front-end (AFE) platforms. Designed to support the entire TSW14xxx series of data-capture and pattern-generation cards (...)
Features
  • Compatible with TSW1400, TSW1405, TSW1406 and TSW14J10, TSW14J50, TSW14J56, and TSW14J57 pattern-generation and data-capture platforms
  • Works with all TI high-speed DAC, ADC, and AFE products
  • Provides time-domain and frequency-domain analysis
  • Supports single-tone, multi-tone, and modulated (...)

Design tools & simulation

SIMULATION MODEL Download
SLLC320A.ZIP (7 KB) - IBIS Model
SIMULATION TOOL Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
CALCULATION TOOL Download
SLAC169.ZIP (33 KB)

CAD/CAE symbols

Package Pins Download
VQFN (RGC) 64 View options

Ordering & quality

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  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

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