ADS62C17

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Dual-Channel, 11-Bit, 200-MSPS Analog-to-Digital Converter (ADC)

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Product details

Parameters

Sample rate (Max) (MSPS) 200 Resolution (Bits) 11 Number of input channels 2 Interface type Parallel LVDS Analog input BW (MHz) 700 Features High Performance Rating Catalog Input range (Vp-p) 2 Power consumption (Typ) (mW) 1081 Architecture Pipeline SNR (dB) 67 ENOB (Bits) 10.8 SFDR (dB) 85 Operating temperature range (C) -40 to 85 Input buffer No open-in-new Find other High-speed ADCs (>10MSPS)

Package | Pins | Size

VQFN (RGC) 64 81 mm² 9 x 9 open-in-new Find other High-speed ADCs (>10MSPS)

Features

  • Maximum Sample Rate: 200 MSPS
  • 11-bit Resolution with No Missing Codes
  • 90 dBc SFDR at Fin = 10 MHz
  • 79.8 dBFS SNR at 125 MHz IF, 20 MHz BW
    using TI proprietary SNRBoost technology
  • Total Power 1.1 W at 200 MSPS
  • 90 dB Cross-talk
  • Double Data Rate (DDR) LVDS and Parallel
    CMOS Output Options
  • Programmable Gain up to 6dB for SNR/SFDR Trade-off
  • DC Offset Correction
  • Gain Tuning Capability in Fine Steps (0.001 dB)
    Allows Channel-to-channel Gain Matching
  • Supports Input Clock Amplitude Down to
    400 mV p-p Differential
  • Internal and External Reference Support
  • 64-QFN Package (9 mm × 9 mm)

open-in-new Find other High-speed ADCs (>10MSPS)

Description

ADS62C17 is a dual channel 11-bit, 200 MSPS A/D converter that combines high dynamic performance and low power consumption in a compact 64 QFN package. This makes it well-suited for multi-carrier, wide band-width communications applications.

ADS62C17 uses TI-proprietary SNRBoost technology that can be used to overcome SNR limitation due to quantization noise for bandwidths less than Nyquist (Fs/2). It includes several useful and commonly used digital functions such as ADC offset correction, gain (0 to 6 dB in steps of 0.5 dB) and gain tuning (in fine steps of 0.001 dB).

The gain option can be used to improve SFDR performance at lower full-scale input ranges. Using the gain tuning capability, each channel’s gain can be set independently to improve channel-to-channel gain matching. The device also includes a dc offset correction loop that can be used to cancel the ADC offset.

Both DDR LVDS (Double Data Rate) and parallel CMOS digital output interfaces are available. It includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. Nevertheless, the device can also be driven with an external reference.

The device is specified over the industrial temperature range (–40°C to 85°C).

open-in-new Find other High-speed ADCs (>10MSPS)
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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 16
Type Title Date
* Datasheet Dual Channel 11 Bit, 200 MSPS ADC with SNRBoost datasheet (Rev. A) Jul. 17, 2009
Technical articles How to achieve fast frequency hopping Mar. 03, 2019
Technical articles RF sampling: Learning more about latency Feb. 09, 2017
Technical articles Why phase noise matters in RF sampling converters Nov. 28, 2016
Technical articles How to minimize filter loss when you drive an ADC Oct. 20, 2016
Application notes Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) May 22, 2015
Application notes Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) Jul. 19, 2013
User guides TSW4200 Demonstration Kit User's Guide (Rev. C) Oct. 31, 2012
Application notes Understanding Low-Amplitude Behavior of 11-bit ADCs Oct. 22, 2011
Application notes Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) Sep. 10, 2010
Application notes Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio Apr. 28, 2009
User guides ADS62PXX EVM User's Guide for EVM Rev. C (Rev. A) Feb. 23, 2009
Application notes CDCE62005 as Clock Solution for High-Speed ADCs Sep. 04, 2008
Application notes CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters Jun. 08, 2008
Application notes Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 Jun. 02, 2008
Application notes QFN Layout Guidelines Jul. 28, 2006

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
99
Description

The TSW1405EVM is a low cost data capture circuit board used to evaluate some of Texas Instruments’ (TI) most popular high speed analog-to-digital converters (ADC).

 

The TSW1405EVM supports a high speed LVDS bus capable of providing 16-bit samples at 1.0 GSPS. The platform supports a 64k sample depth (...)

Features
  • Simple 16-bit waveform capture from many of TI’s high speed ADC EVM’s
  • Supports 64k sample depth at up to 1.0 GSPS LVDS I/O rates
  • LatticeECP3 high speed mini FPGA
  • Analyzes up to 8 channels concurrently
  • Single mini USB cable for power and data
  • Utilizes an intuitive/easy-to-use GUI package
  • Industry’s (...)
  • Software development

    PROGRAMMING TOOLS Download
    SUPPORT SOFTWARE Download
    High-speed data converter pro software
    DATACONVERTERPRO-SW This high-speed data converter pro GUI is a PC (Windows® XP/7 compatible) program designed to aid in evaluation of most TI high-speed data converter and analog front-end (AFE) platforms. Designed to support the entire TSW14xxx series of data-capture and pattern-generation cards (...)
    Features
    • Compatible with TSW1400, TSW1405, TSW1406 and TSW14J10, TSW14J50, TSW14J56, and TSW14J57 pattern-generation and data-capture platforms
    • Works with all TI high-speed DAC, ADC, and AFE products
    • Provides time-domain and frequency-domain analysis
    • Supports single-tone, multi-tone, and modulated (...)
    SUPPORT SOFTWARE Download
    SBAC120.ZIP (262219 KB)

    Design tools & simulation

    SIMULATION MODELS Download
    SBAM015.TSM (14 KB) - TINA-TI Spice Model
    SIMULATION MODELS Download
    SBAM016.TSC (106 KB) - TINA-TI Reference Design
    SIMULATION MODELS Download
    SLWC088B.ZIP (653 KB) - IBIS Model
    SIMULATION TOOLS Download
    PSpice® for TI design and simulation tool
    PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
    Features
    • Leverages Cadence PSpice Technology
    • Preinstalled library with a suite of digital models to enable worst-case timing analysis
    • Dynamic updates ensure you have access to most current device models
    • Optimized for simulation speed without loss of accuracy
    • Supports simultaneous analysis of multiple products
    • (...)
    CALCULATION TOOLS Download
    Jitter and SNR Calculator for ADCs
    JITTER-SNR-CALC JITTER-SNR-CALC can be used for calculating theoretical Signal to Noise (SNR) performance of ADCs based on input frequency and clock jitter.
    DESIGN TOOLS Download
    SBAC119B.ZIP (3547 KB)

    CAD/CAE symbols

    Package Pins Download
    VQFN (RGC) 64 View options

    Ordering & quality

    Support & training

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