ADS58C28

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Dual-Channel, 11-Bit, 200-MSPS Analog-to-Digital Converter (ADC)

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Product details

Parameters

Sample rate (Max) (MSPS) 200 Resolution (Bits) 11 Number of input channels 2 Interface type Parallel CMOS, Parallel LVDS Analog input BW (MHz) 600 Features High Performance Rating Catalog Input range (Vp-p) 2 Power consumption (Typ) (mW) 505 Architecture Pipeline SNR (dB) 66.8 ENOB (Bits) 10.7 SFDR (dB) 84 Operating temperature range (C) -40 to 85 Input buffer No open-in-new Find other High-speed ADCs (>10MSPS)

Package | Pins | Size

VQFN (RGC) 64 81 mm² 9 x 9 open-in-new Find other High-speed ADCs (>10MSPS)

Features

  • Maximum Sample Rate: 200MSPS
  • High Dynamic Performance:
    • 83dBc SFDR at 140MHz
    • 72.5dBFS SNR with 60MHz BW Using SNRBoost3G Technology
  • SNRBoost3G Highlights:
    • Supports Wide Bandwidth (up to 60MHz)
    • Programmable Bandwidths:
      20MHz, 30MHz, and 40MHz
    • Flat Noise Floor within the Band
    • Independent SNRBoost3G Coefficients for Both Channels
  • Output Interface:
    • Double Data Rate (DDR) LVDS with Programmable Swing and Strength:
      • Standard Swing: 350mV
      • Low Swing: 200mV
      • Default Strength: 100Ω termination
      • 2× Strength: 50Ω termination
    • Compatible with GC6016
    • 1.8V Parallel CMOS Interface Also Supported
  • Ultralow Power with Single 1.8V Supply:
    • 470mW Total Power
    • 710mW Total Power (200MSPS) with SNRBoost3G on Both Channels
  • Programmable Gain up to 6dB for
    SNR/SFDR Trade-off
  • DC Offset Correction
  • Supports Low Input Clock Amplitude
  • Package: QFN-64 (9mm × 9mm)

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open-in-new Find other High-speed ADCs (>10MSPS)

Description

The ADS58C28 is a dual-channel, 11-bit analog-to-digital converter (ADC) with sampling rates up to 200MSPS. The device uses innovative design techniques to achieve high dynamic performance, while consuming extremely low power at 1.8V supply. This architecture makes it well-suited for multi-carrier, wide bandwidth communications applications.

The ADS58C28 uses third-generation SNRBoost3G technology to overcome SNR limitation as a result of quantization noise (for bandwidths less than Nyquist, fS/2). Enhancements in the SNRBoost3G technology allow support for SNR improvements over wide bandwidths (up to 60MHz). In addition, separate SNRBoost3G coefficients can also be programmed for each channel.

The device has a digital gain function that can be used to improve SFDR performance at lower full-scale input ranges. It includes a dc offset correction loop that can be used to cancel the ADC offset. The digital outputs of all channels are output as double data rate (DDR) low-voltage differential signaling (LVDS) together with an LVDS clock output. The low data rate of this interface (400MBPS at 200MSPS sample rate) makes it possible to use low-cost field-programmable gate array (FPGA)-based receivers. The strength of the LVDS output buffers can be increased to support 50Ω differential termination. This increase allows the output clock signal to be connected to two separate receiver chips with an effective 50Ω termination (such as the two clock ports of the GC5330). The same digital output pins can also be configured as a parallel 1.8V CMOS interface.

The device includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. The ADS58C28 is specified over the industrial temperature range (–40°C to +85°C).

open-in-new Find other High-speed ADCs (>10MSPS)
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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 17
Type Title Date
* Datasheet Dual Channel IF Receiver with SNRBoost3G datasheet (Rev. B) Oct. 29, 2010
Technical articles Keys to quick success using high-speed data converters Oct. 13, 2020
Technical articles How to achieve fast frequency hopping Mar. 03, 2019
Technical articles RF sampling: Learning more about latency Feb. 09, 2017
Technical articles Why phase noise matters in RF sampling converters Nov. 28, 2016
Application note Band-Pass Filter Design Techniques for High-Speed ADCs Feb. 27, 2012
Application note High-Speed, Analog-to-Digital Converter Basics Jan. 11, 2012
Application note Power Supply Design for the ADS41xx (Rev. A) Dec. 29, 2011
Application note Understanding Low-Amplitude Behavior of 11-bit ADCs Oct. 22, 2011
User guide ADS58C28 EVM User’s Guide Oct. 28, 2010
Application note Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) Sep. 10, 2010
Application note Using Windowing With SNRBoost 3G Technology Aug. 30, 2010
Application note Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio Apr. 28, 2009
Application note CDCE62005 as Clock Solution for High-Speed ADCs Sep. 04, 2008
Application note CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters Jun. 08, 2008
Application note Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 Jun. 02, 2008
Application note QFN Layout Guidelines Jul. 28, 2006

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
document-generic User guide
Description

The ADS58C28EVM is a circuit board that allows designers to evaluate the performance of Texas Instruments' ADS58C28 device, a dual channel 11-bit 200 MSPS analog to digital converter featuring TI's SNRBoost technology. The ADC EVM features a DDR LVDS data output which is compatible with TI's TSW1200 (...)

EVALUATION BOARD Download
document-generic User guide
99
Description

The TSW1405EVM is a low cost data capture circuit board used to evaluate some of Texas Instruments’ (TI) most popular high speed analog-to-digital converters (ADC).

 

The TSW1405EVM supports a high speed LVDS bus capable of providing 16-bit samples at 1.0 GSPS. The platform supports a 64k sample depth (...)

Features
  • Simple 16-bit waveform capture from many of TI’s high speed ADC EVM’s
  • Supports 64k sample depth at up to 1.0 GSPS LVDS I/O rates
  • LatticeECP3 high speed mini FPGA
  • Analyzes up to 8 channels concurrently
  • Single mini USB cable for power and data
  • Utilizes an intuitive/easy-to-use GUI package
  • Industry’s (...)
  • Software development

    GUI FOR EVALUATION MODULE (EVM) Download
    SBAC113B.ZIP (129504 KB)
    SUPPORT SOFTWARE Download
    High-speed data converter pro software
    DATACONVERTERPRO-SW This high-speed data converter pro GUI is a PC (Windows® XP/7 compatible) program designed to aid in evaluation of most TI high-speed data converter and analog front-end (AFE) platforms. Designed to support the entire TSW14xxx series of data-capture and pattern-generation cards (...)
    Features
    • Compatible with TSW1400, TSW1405, TSW1406 and TSW14J10, TSW14J50, TSW14J56, and TSW14J57 pattern-generation and data-capture platforms
    • Works with all TI high-speed DAC, ADC, and AFE products
    • Provides time-domain and frequency-domain analysis
    • Supports single-tone, multi-tone, and modulated (...)
    SUPPORT SOFTWARE Download
    SBAC120.ZIP (262219 KB)

    Design tools & simulation

    SIMULATION TOOL Download
    PSpice® for TI design and simulation tool
    PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
    Features
    • Leverages Cadence PSpice Technology
    • Preinstalled library with a suite of digital models to enable worst-case timing analysis
    • Dynamic updates ensure you have access to most current device models
    • Optimized for simulation speed without loss of accuracy
    • Supports simultaneous analysis of multiple products
    • (...)
    CALCULATION TOOL Download
    Jitter and SNR Calculator for ADCs
    JITTER-SNR-CALC JITTER-SNR-CALC can be used for calculating theoretical Signal to Noise (SNR) performance of ADCs based on input frequency and clock jitter.
    DESIGN TOOL Download
    SBAC119B.ZIP (3547 KB)
    SCHEMATIC Download
    SLAC459B.ZIP (6548 KB)

    CAD/CAE symbols

    Package Pins Download
    VQFN (RGC) 64 View options

    Ordering & quality

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    • Ongoing reliability monitoring

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