Product details

Sample rate (Max) (MSPS) 25 Resolution (Bits) 14 Number of input channels 2 Interface type Serial LVDS Analog input BW (MHz) 540 Features Low Power Rating Catalog Input range (Vp-p) 2 Power consumption (Typ) (mW) 120 Architecture Pipeline SNR (dB) 73.8 ENOB (Bits) 11.9 SFDR (dB) 94 Operating temperature range (C) -40 to 85 Input buffer No
Sample rate (Max) (MSPS) 25 Resolution (Bits) 14 Number of input channels 2 Interface type Serial LVDS Analog input BW (MHz) 540 Features Low Power Rating Catalog Input range (Vp-p) 2 Power consumption (Typ) (mW) 120 Architecture Pipeline SNR (dB) 73.8 ENOB (Bits) 11.9 SFDR (dB) 94 Operating temperature range (C) -40 to 85 Input buffer No
VQFN (RGZ) 48 49 mm² 7 x 7
  • Dual Channel
  • 14-Bit Resolution
  • Single Supply: 1.8 V
  • Serial LVDS Interface (SLVDS)
  • Flexible Input Clock Buffer with Divide-by-1, -2, -4
  • SNR = 72.4 dBFS, SFDR = 87 dBc at
    fIN = 70 MHz
  • Ultra-Low Power Consumption:
    • 116 mW/Ch at 125 MSPS
  • Channel Isolation: 105 dB
  • Internal Dither and Chopper
  • Support for Multi-Chip Synchronization
  • Pin-to-Pin Compatible with 12-Bit Version
  • Package: VQFN-48 (7 mm × 7 mm)
  • Dual Channel
  • 14-Bit Resolution
  • Single Supply: 1.8 V
  • Serial LVDS Interface (SLVDS)
  • Flexible Input Clock Buffer with Divide-by-1, -2, -4
  • SNR = 72.4 dBFS, SFDR = 87 dBc at
    fIN = 70 MHz
  • Ultra-Low Power Consumption:
    • 116 mW/Ch at 125 MSPS
  • Channel Isolation: 105 dB
  • Internal Dither and Chopper
  • Support for Multi-Chip Synchronization
  • Pin-to-Pin Compatible with 12-Bit Version
  • Package: VQFN-48 (7 mm × 7 mm)

The ADC324x are a high-linearity, ultra-low power, dual-channel, 14-bit, 25-MSPS to 125-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock architecture design and the SYSREF input enables complete system synchronization. The ADC324x family supports serial low-voltage differential signaling (LVDS) in order to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where each ADC data are serialized and output over two LVDS pairs. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 14-bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.

The ADC324x are a high-linearity, ultra-low power, dual-channel, 14-bit, 25-MSPS to 125-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock architecture design and the SYSREF input enables complete system synchronization. The ADC324x family supports serial low-voltage differential signaling (LVDS) in order to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where each ADC data are serialized and output over two LVDS pairs. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 14-bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.

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Technical documentation

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Type Title Date
* Data sheet ADC324x Dual-Channel, 14-Bit, 25-MSPS to 125-MSPS, Analog-to-Digital Converters datasheet (Rev. C) 22 Mar 2016
Technical article How smart AFEs offer an integrated analog solution for thermoelectric cooling control 04 Jan 2022
Technical article Keys to quick success using high-speed data converters 13 Oct 2020
Technical article How to achieve fast frequency hopping 03 Mar 2019
User guide ADC3xxxEVM and ADC3xJxxEVM User's Guide (Rev. D) 24 Aug 2018
Technical article RF sampling: Learning more about latency 09 Feb 2017

Design & development

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Evaluation board

ADC3241EVM — ADC3241 Dual-Channel, 14-Bit, 25-MSPS Analog-to-Digital Converter Evaluation Module

The ADC3241 EVM demonstrates the performance of a low power dual 25Msps 14 bit ADC. It includes the ADC3241 device and TI voltage regulators to provide the necessary voltages. The input for the ADC is by default connected to the transformer input which can be connected to a 50 ohm single ended (...)

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Support software

DATACONVERTERPRO-SW — High-speed data converter pro software

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter and analog front-end (AFE) platforms. Designed to support the entire TSW14xxx series of data-capture and pattern-generation cards, (...)
Simulation model

ADC3244 IBIS Model

SLAM241.ZIP (31 KB) - IBIS Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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VQFN (RGZ) 48 View options

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