12-Bit, 125-MSPS Analog-to-Digital Converter (ADC)
Product details
Parameters
Package | Pins | Size
Features
- Resolution: 12-Bit, 125MSPS
- Integrated High-Impedance
Analog Input Buffer:- Input Capacitance at dc: 3.5pF
- Input Resistance at dc: 10kΩ
- Maximum Sample Rate: 125MSPS
- Ultralow Power:
- 1.8V Analog Power: 114mW
- 3.3V Buffer Power: 96mW
- I/O Power: 100mW (DDR LVDS)
- High Dynamic Performance:
- SNR: 68.3dBFS at 170MHz
- SFDR: 87dBc at 170MHz
- Output Interface:
- Double Data Rate (DDR) LVDS with Programmable Swing and Strength:
- Standard Swing: 350mV
- Low Swing: 200mV
- Default Strength: 100Ω Termination
- 2x Strength: 50Ω Termination
- 1.8V Parallel CMOS Interface Also Supported
- Double Data Rate (DDR) LVDS with Programmable Swing and Strength:
- Programmable Gain for SNR/SFDR Trade-Off
- DC Offset Correction
- Supports Low Input Clock Amplitude
- Package: QFN-48 (7mm × 7mm)
PowerPAD is a trademark of Texas Instruments, Incorporated.
All other trademarks are the property of their respective owners.
Description
The ADS41B25 is a member of the ultralow-power ADS4xxx analog-to-digital converter (ADC) family, featuring integrated analog input buffers. This device uses innovative design techniques to achieve high dynamic performance, while consuming extremely low power. The analog input pins have buffers, with the benefits of constant performance and input impedance across a wide frequency range. The device is well-suited for multi-carrier, wide bandwidth communications applications such as PA linearization.
The ADS41B25 has features such as digital gain and offset correction. The gain option can be used to improve SFDR performance at lower full-scale input ranges, especially at high input frequencies. The integrated dc offset correction loop can be used to estimate and cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled-down power with no loss in performance.
The device supports both double data rate (DDR) low-voltage differential signaling (LVDS) and parallel CMOS digital output interfaces. The low data rate of the DDR LVDS interface (maximum 500MBPS) makes it possible to use low-cost field-programmable gate array (FPGA)-based receivers. The device has a low-swing LVDS mode that can be used to further reduce the power consumption. The strength of the LVDS output buffers can also be increased to support 50Ω differential termination.
The device is available in a compact QFN-48 package and is specified over the industrial temperature range (–40°C to +85°C).
Technical documentation
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
Description
The ADS41B25EVM is a circuit board that allows designers to evaluate the performance of Texas Instruments‘ ADS41B25 device, an extremely low power 12-bit 125 MSPS analog to digital converter with integrated high-impedance input buffer. The ADC features a configurable parallel DDR LVDS or CMOS (...)
Features
Description
The TSW1405EVM is a low cost data capture circuit board used to evaluate some of Texas Instrumentsâ (TI) most popular high speed analog-to-digital converters (ADC).
ÂThe TSW1405EVM supports a high speed LVDS bus capable of providing 16-bit samples at 1.0 GSPS. The platform supports a 64k sample depth (...)
Features
Description
The TSW3085 Evalutaion Module is a circuit board that allows system designers to evaluate the combined performance of Texas Instruments' transmit signal chain with the LMK04806B (formally National Semiconductor) low noise clock generator/jitter cleaner. For ease of use as a complete RF transmit (...)
Features
Software development
Features
- Compatible with TSW1400, TSW1405, TSW1406 and TSW14J10, TSW14J50, TSW14J56, and TSW14J57 pattern-generation and data-capture platforms
- Works with all TI high-speed DAC, ADC, and AFE products
- Provides time-domain and frequency-domain analysis
- Supports single-tone, multi-tone, and modulated (...)
Design tools & simulation
Features
- Leverages Cadence PSpice Technology
- Preinstalled library with a suite of digital models to enable worst-case timing analysis
- Dynamic updates ensure you have access to most current device models
- Optimized for simulation speed without loss of accuracy
- Supports simultaneous analysis of multiple products
- (...)
CAD/CAE symbols
Package | Pins | Download |
---|---|---|
VQFN (RGZ) | 48 | View options |
Ordering & quality
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
Recommended products may have parameters, evaluation modules or reference designs related to this TI product.
Support & training
TI E2E™ forums with technical support from TI engineers
Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.
If you have questions about quality, packaging or ordering TI products, see TI support.