Quad-Channel, 11-Bit, 200-MSPS Analog-to-Digital Converter (ADC)
Product details
Parameters
Package | Pins | Size
Features
- Maximum Sample Rate: 200 MSPS
- High Dynamic Performance
- SFDR 82 dBc at 140 MHz
- 72.3 dBFS SNR in 60 MHz BW Using SNRBoost3G technology
- SNRBoost3G Highlights
- Supports Wide Bandwidth up to 60 MHz
- Programmable Bandwidths – 60 MHz, 40 MHz, 30 MHz, 20 MHz
- Flat Noise Floor within the Band
- Independent SNRBoost3G Coefficients for Every Channel
- Output Interface
- Double Data Rate (DDR) LVDS with Programmable Swing and Strength
- Standard Swing: 350mV
- Low Swing: 200mV
- Default Strength: 100
Termination
- 2x Strength: 50
Termination
- 1.8V Parallel CMOS Interface Also Supported
- Double Data Rate (DDR) LVDS with Programmable Swing and Strength
- Ultra-Low Power with Single 1.8V Supply
- 0.9W Total Power
- 1.32 W Total Power (200 MSPS) with SNRBoost3G on all 4 Channels
- 1.12 W Total Power (200 MSPS) with SNRBoost3G on 2 Channels
- Programmable Gain up to 6dB for SNR/SFDR Trade-Off
- DC Offset Correction
- Supports Low Input Clock Amplitude
- 80-TQFP Package
Description
The ADS58C48 is a quad channel 11-bit A/D converter with sampling rate up to 200 MSPS. It uses innovative design techniques to achieve high dynamic performance, while consuming extremely low power at 1.8V supply. This makes it well-suited for multi-carrier, wide band-width communications applications.
The ADS58C48 uses third-generation SNRBoost3G technology to overcome SNR limitation due to quantization noise (for bandwidths < Nyquist, Fs/2). Enhancements in the SNRBoost3G technology allow support for SNR improvements over wide bandwidths (up to 60 MHz). In addition, separate SNRBoost3G coefficients can be programmed for each channel.
The device has digital gain function that can be used to improve SFDR performance at lower full-scale input ranges. It includes a dc offset correction loop that can be used to cancel the ADC offset.
The digital outputs of all channels are output as DDR LVDS (Double Data Rate) together with an LVDS clock output. The low data rate of this interface (400Mbps at 200 MSPS sample rate) makes it possible to use low-cost FPGA-based receivers. The strength of the LVDS output buffers can be increased to support 50 ohms differential termination. This allows the output clock signal to be connected to two separate receiver chips with an effective 50 termination (such as the two clock ports of the GC5330).
The same digital output pins can also be configured as a parallel 1.8V CMOS interface.
It includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. The device is specified over the industrial temperature range (–40°C to 85°C).
Technical documentation
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
Description
The ADS58C28EVM is a circuit board that allows designers to evaluate the performance of Texas Instruments' ADS58C28 device, a dual channel 11-bit 200 MSPS analog to digital converter featuring TI's SNRBoost technology. The ADC EVM features a DDR LVDS data output which is compatible with TI's TSW1200 (...)
Description
The TSW1405EVM is a low cost data capture circuit board used to evaluate some of Texas Instrumentsâ (TI) most popular high speed analog-to-digital converters (ADC).
ÂThe TSW1405EVM supports a high speed LVDS bus capable of providing 16-bit samples at 1.0 GSPS. The platform supports a 64k sample depth (...)
Features
Software development
Features
- Compatible with TSW1400, TSW1405, TSW1406 and TSW14J10, TSW14J50, TSW14J56, and TSW14J57 pattern-generation and data-capture platforms
- Works with all TI high-speed DAC, ADC, and AFE products
- Provides time-domain and frequency-domain analysis
- Supports single-tone, multi-tone, and modulated (...)
Design tools & simulation
Features
- Leverages Cadence PSpice Technology
- Preinstalled library with a suite of digital models to enable worst-case timing analysis
- Dynamic updates ensure you have access to most current device models
- Optimized for simulation speed without loss of accuracy
- Supports simultaneous analysis of multiple products
- (...)
CAD/CAE symbols
Package | Pins | Download |
---|---|---|
HTQFP (PFP) | 80 | View options |
Ordering & quality
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
Recommended products may have parameters, evaluation modules or reference designs related to this TI product.
Support & training
TI E2E™ forums with technical support from TI engineers
Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.
If you have questions about quality, packaging or ordering TI products, see TI support.