Product details

Sample rate (Max) (MSPS) 200 Resolution (Bits) 11 Number of input channels 4 Interface type Parallel CMOS, Parallel LVDS Analog input BW (MHz) 600 Features Low Power Rating Catalog Input range (Vp-p) 2 Power consumption (Typ) (mW) 900 Architecture Pipeline SNR (dB) 66.7 ENOB (Bits) 10.7 SFDR (dB) 84 Operating temperature range (C) -40 to 85 Input buffer No
Sample rate (Max) (MSPS) 200 Resolution (Bits) 11 Number of input channels 4 Interface type Parallel CMOS, Parallel LVDS Analog input BW (MHz) 600 Features Low Power Rating Catalog Input range (Vp-p) 2 Power consumption (Typ) (mW) 900 Architecture Pipeline SNR (dB) 66.7 ENOB (Bits) 10.7 SFDR (dB) 84 Operating temperature range (C) -40 to 85 Input buffer No
HTQFP (PFP) 80 196 mm² 14 x 14
  • Maximum Sample Rate: 200 MSPS
  • High Dynamic Performance
    • SFDR 82 dBc at 140 MHz
    • 72.3 dBFS SNR in 60 MHz BW Using SNRBoost3G technology
  • SNRBoost3G Highlights
    • Supports Wide Bandwidth up to 60 MHz
    • Programmable Bandwidths – 60 MHz, 40 MHz, 30 MHz, 20 MHz
    • Flat Noise Floor within the Band
    • Independent SNRBoost3G Coefficients for Every Channel
  • Output Interface
    • Double Data Rate (DDR) LVDS with Programmable Swing and Strength
      • Standard Swing: 350mV
      • Low Swing: 200mV
      • Default Strength: 100 Termination
      • 2x Strength: 50 Termination
    • 1.8V Parallel CMOS Interface Also Supported
  • Ultra-Low Power with Single 1.8V Supply
    • 0.9W Total Power
    • 1.32 W Total Power (200 MSPS) with SNRBoost3G on all 4 Channels
    • 1.12 W Total Power (200 MSPS) with SNRBoost3G on 2 Channels
  • Programmable Gain up to 6dB for SNR/SFDR Trade-Off
  • DC Offset Correction
  • Supports Low Input Clock Amplitude
  • 80-TQFP Package

  • Maximum Sample Rate: 200 MSPS
  • High Dynamic Performance
    • SFDR 82 dBc at 140 MHz
    • 72.3 dBFS SNR in 60 MHz BW Using SNRBoost3G technology
  • SNRBoost3G Highlights
    • Supports Wide Bandwidth up to 60 MHz
    • Programmable Bandwidths – 60 MHz, 40 MHz, 30 MHz, 20 MHz
    • Flat Noise Floor within the Band
    • Independent SNRBoost3G Coefficients for Every Channel
  • Output Interface
    • Double Data Rate (DDR) LVDS with Programmable Swing and Strength
      • Standard Swing: 350mV
      • Low Swing: 200mV
      • Default Strength: 100 Termination
      • 2x Strength: 50 Termination
    • 1.8V Parallel CMOS Interface Also Supported
  • Ultra-Low Power with Single 1.8V Supply
    • 0.9W Total Power
    • 1.32 W Total Power (200 MSPS) with SNRBoost3G on all 4 Channels
    • 1.12 W Total Power (200 MSPS) with SNRBoost3G on 2 Channels
  • Programmable Gain up to 6dB for SNR/SFDR Trade-Off
  • DC Offset Correction
  • Supports Low Input Clock Amplitude
  • 80-TQFP Package

The ADS58C48 is a quad channel 11-bit A/D converter with sampling rate up to 200 MSPS. It uses innovative design techniques to achieve high dynamic performance, while consuming extremely low power at 1.8V supply. This makes it well-suited for multi-carrier, wide band-width communications applications.

The ADS58C48 uses third-generation SNRBoost3G technology to overcome SNR limitation due to quantization noise (for bandwidths < Nyquist, Fs/2). Enhancements in the SNRBoost3G technology allow support for SNR improvements over wide bandwidths (up to 60 MHz). In addition, separate SNRBoost3G coefficients can be programmed for each channel.

The device has digital gain function that can be used to improve SFDR performance at lower full-scale input ranges. It includes a dc offset correction loop that can be used to cancel the ADC offset.

The digital outputs of all channels are output as DDR LVDS (Double Data Rate) together with an LVDS clock output. The low data rate of this interface (400Mbps at 200 MSPS sample rate) makes it possible to use low-cost FPGA-based receivers. The strength of the LVDS output buffers can be increased to support 50 ohms differential termination. This allows the output clock signal to be connected to two separate receiver chips with an effective 50 termination (such as the two clock ports of the GC5330).

The same digital output pins can also be configured as a parallel 1.8V CMOS interface.

It includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. The device is specified over the industrial temperature range (–40°C to 85°C).

The ADS58C48 is a quad channel 11-bit A/D converter with sampling rate up to 200 MSPS. It uses innovative design techniques to achieve high dynamic performance, while consuming extremely low power at 1.8V supply. This makes it well-suited for multi-carrier, wide band-width communications applications.

The ADS58C48 uses third-generation SNRBoost3G technology to overcome SNR limitation due to quantization noise (for bandwidths < Nyquist, Fs/2). Enhancements in the SNRBoost3G technology allow support for SNR improvements over wide bandwidths (up to 60 MHz). In addition, separate SNRBoost3G coefficients can be programmed for each channel.

The device has digital gain function that can be used to improve SFDR performance at lower full-scale input ranges. It includes a dc offset correction loop that can be used to cancel the ADC offset.

The digital outputs of all channels are output as DDR LVDS (Double Data Rate) together with an LVDS clock output. The low data rate of this interface (400Mbps at 200 MSPS sample rate) makes it possible to use low-cost FPGA-based receivers. The strength of the LVDS output buffers can be increased to support 50 ohms differential termination. This allows the output clock signal to be connected to two separate receiver chips with an effective 50 termination (such as the two clock ports of the GC5330).

The same digital output pins can also be configured as a parallel 1.8V CMOS interface.

It includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. The device is specified over the industrial temperature range (–40°C to 85°C).

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Technical documentation

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Type Title Date
* Data sheet Quad Channel IF Receiver with SNRBoost 3G datasheet 27 May 2010
Technical article How smart AFEs offer an integrated analog solution for thermoelectric cooling control 04 Jan 2022
Technical article Keys to quick success using high-speed data converters 13 Oct 2020
Technical article How to achieve fast frequency hopping 03 Mar 2019
Technical article RF sampling: Learning more about latency 09 Feb 2017
Application note Band-Pass Filter Design Techniques for High-Speed ADCs 27 Feb 2012
Application note High-Speed, Analog-to-Digital Converter Basics 11 Jan 2012
Application note Power Supply Design for the ADS41xx (Rev. A) 29 Dec 2011
Application note Understanding Low-Amplitude Behavior of 11-bit ADCs 22 Oct 2011
Application note Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) 10 Sep 2010
Application note Using Windowing With SNRBoost 3G Technology 30 Aug 2010
User guide ADS58C48EVM User's Guide 19 Apr 2010
Application note Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio 28 Apr 2009
Application note CDCE62005 as Clock Solution for High-Speed ADCs 04 Sep 2008
Application note CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters 08 Jun 2008
Application note Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 02 Jun 2008

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

ADS58C28EVM — ADS58C28 Dual-Channel, 11-Bit, 200-MSPS Analog-to-Digital Converter Evaluation Module

The ADS58C28EVM is a circuit board that allows designers to evaluate the performance of Texas Instruments' ADS58C28 device, a dual channel 11-bit 200 MSPS analog to digital converter featuring TI's SNRBoost technology. The ADC EVM features a DDR LVDS data output which is compatible with TI's (...)

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Evaluation board

TSW1405EVM — Data converter data capture evaluation module with 8 LVDS lanes up to 1.0 Gbps

The TSW1405EVM is a low cost data capture circuit board used to evaluate some of Texas Instruments’ (TI) most popular high speed analog-to-digital converters (ADC).

 

The TSW1405EVM supports a high speed LVDS bus capable of providing 16-bit samples at 1.0 GSPS. The platform supports a 64k sample (...)

Out of stock on TI.com
Support software

ADS58C48SPI-SW — ADS58C48 SPI Software

The ADS58C28 EVM software GUI allows for programming control of the ADS58C48.
Support software

DATACONVERTERPRO-SW — High-speed data converter pro software

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter and analog front-end (AFE) platforms. Designed to support the entire TSW14xxx series of data-capture and pattern-generation cards, (...)
Support software

TIGAR Support Files

SBAC120.ZIP (262219 KB)
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Calculation tool

JITTER-SNR-CALC — Jitter and SNR Calculator for ADCs

JITTER-SNR-CALC can be used for calculating theoretical Signal to Noise (SNR) performance of ADCs based on input frequency and clock jitter.
Schematic

TSW2110EVM Design Package board rev B

SLAR064.ZIP (1580 KB)
PCB layout

TSW2200EVM Design Package PCB

SLWR039.ZIP (3979 KB)
Package Pins Download
HTQFP (PFP) 80 View options

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