Product details

Sample rate (Max) (MSPS) 105 Resolution (Bits) 14 Number of input channels 4 Interface type Serial LVDS Analog input BW (MHz) 500 Features High Performance Rating Catalog Input range (Vp-p) 2 Power consumption (Typ) (mW) 1350 Architecture Pipeline SNR (dB) 73.8 ENOB (Bits) 11.7 SFDR (dB) 91 Operating temperature range (C) -40 to 85 Input buffer No
Sample rate (Max) (MSPS) 105 Resolution (Bits) 14 Number of input channels 4 Interface type Serial LVDS Analog input BW (MHz) 500 Features High Performance Rating Catalog Input range (Vp-p) 2 Power consumption (Typ) (mW) 1350 Architecture Pipeline SNR (dB) 73.8 ENOB (Bits) 11.7 SFDR (dB) 91 Operating temperature range (C) -40 to 85 Input buffer No
VQFN (RGC) 64 81 mm² 9.0 x 9.0
  • Maximum Sample Rate: 125 MSPS
  • 14-Bit Resolution with No Missing Codes
  • Simultaneous Sample and Hold
  • 3.5dB Coarse Gain and up to 6dB Programmable Fine Gain for SFDR/SNR Trade-Off
  • Serialized LVDS Outputs with Programmable Internal Termination Option
  • Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs and Amplitude down to 400 mVPP
  • Internal Reference with External Reference Support
  • No External Decoupling Required for References
  • 3.3-V Analog and Digital Supply
  • 64 QFN Package (9 mm × 9 mm)
  • Pin Compatible 12-Bit Family (ADS642X - SLAS532A)
  • Feature Compatible Dual Channel Family (ADS624X - SLAS542A, ADS644X - SLAS543A)
  • APPLICATIONS
    • Base-Station IF Receivers
    • Diversity Receivers
    • Medical Imaging
    • Test Equipment
  • Maximum Sample Rate: 125 MSPS
  • 14-Bit Resolution with No Missing Codes
  • Simultaneous Sample and Hold
  • 3.5dB Coarse Gain and up to 6dB Programmable Fine Gain for SFDR/SNR Trade-Off
  • Serialized LVDS Outputs with Programmable Internal Termination Option
  • Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs and Amplitude down to 400 mVPP
  • Internal Reference with External Reference Support
  • No External Decoupling Required for References
  • 3.3-V Analog and Digital Supply
  • 64 QFN Package (9 mm × 9 mm)
  • Pin Compatible 12-Bit Family (ADS642X - SLAS532A)
  • Feature Compatible Dual Channel Family (ADS624X - SLAS542A, ADS644X - SLAS543A)
  • APPLICATIONS
    • Base-Station IF Receivers
    • Diversity Receivers
    • Medical Imaging
    • Test Equipment

The ADS6445/ADS6444/ADS6443/ADS6442 (ADS644X) is a family of high performance 14-bit 125/105/80/65 MSPS quad channel A-D converters. Serial LVDS data outputs reduce the number of interface lines, resulting in a compact 64-pin QFN package (9 mm × 9 mm) that allows for high system integration density. The device includes 3.5dB coarse gain option that can be used to improve SFDR performance with little degradation in SNR. In addition to the coarse gain, fine gain options also exist, programmable in 1dB steps up to 6dB.

The output interface is 2-wire, where each ADC data is serialized and output over two LVDS pairs. This makes it possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1Gbps easing receiver design. The ADS644X also includes the traditional 1-wire interface that can be used at lower sampling frequencies.

An internal phase lock loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock. The bit clock is used to serialize the 14-bit data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.

The LVDS output buffers have features such as programmable LVDS currents, current doubling modes and internal termination options. These can be used to widen eye-openings and improve signal integrity, easing capture by the receiver.

The ADC channel outputs can be transmitted either as MSB or LSB first and 2s complement or straight binary.

The ADS644X has internal references, but can also support an external reference mode. The device is specified over the industrial temperature range (–40°C to 85°C).

The ADS6445/ADS6444/ADS6443/ADS6442 (ADS644X) is a family of high performance 14-bit 125/105/80/65 MSPS quad channel A-D converters. Serial LVDS data outputs reduce the number of interface lines, resulting in a compact 64-pin QFN package (9 mm × 9 mm) that allows for high system integration density. The device includes 3.5dB coarse gain option that can be used to improve SFDR performance with little degradation in SNR. In addition to the coarse gain, fine gain options also exist, programmable in 1dB steps up to 6dB.

The output interface is 2-wire, where each ADC data is serialized and output over two LVDS pairs. This makes it possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1Gbps easing receiver design. The ADS644X also includes the traditional 1-wire interface that can be used at lower sampling frequencies.

An internal phase lock loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock. The bit clock is used to serialize the 14-bit data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.

The LVDS output buffers have features such as programmable LVDS currents, current doubling modes and internal termination options. These can be used to widen eye-openings and improve signal integrity, easing capture by the receiver.

The ADC channel outputs can be transmitted either as MSB or LSB first and 2s complement or straight binary.

The ADS644X has internal references, but can also support an external reference mode. The device is specified over the industrial temperature range (–40°C to 85°C).

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Technical documentation

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Type Title Date
* Data sheet QUAD CHANNEL, 14-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS OUTPUTS datasheet (Rev. B) 16 Dec 2009
Application note QFN and SON PCB Attachment (Rev. B) PDF | HTML 24 Aug 2018
Application note Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) 22 May 2015
Application note Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) 19 Jul 2013
More literature TI and Altera Ease Design Process with Compatible Evaluation Tools 25 Apr 2011
More literature TI and Xilinx Ease Design Process with Compatible Evaluation Tools 25 Apr 2011
Application note Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) 10 Sep 2010
Application note Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio 28 Apr 2009
Application note CDCE62005 as Clock Solution for High-Speed ADCs 04 Sep 2008
EVM User's guide TSW1200EVM: High Speed LVDS Deserializer and Analysis System (Rev. A) 27 Aug 2008
Application note CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters 08 Jun 2008
Application note Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 02 Jun 2008
User guide ADS6245EVM and Lattice ECP2/M Interface Demo User Guide 14 Jan 2008
EVM User's guide ADS64XX EVM User's Guide 16 Apr 2007
Application note QFN Layout Guidelines 28 Jul 2006

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