11-Bit, 200-MSPS Analog-to-Digital Converter (ADC)


Product details


Sample rate (Max) (MSPS) 200 Resolution (Bits) 11 Number of input channels 1 Analog input BW (MHz) 550 Features Low Power Rating Catalog Input range (Vp-p) 2 Power consumption (Typ) (mW) 310 Architecture Pipeline SNR (dB) 66.3 ENOB (Bits) 10.6 SFDR (dB) 87.5 Operating temperature range (C) -40 to 85 Input buffer Yes open-in-new Find other High-speed ADCs (>10MSPS)

Package | Pins | Size

VQFN (RGZ) 48 49 mm² 7 x 7 open-in-new Find other High-speed ADCs (>10MSPS)


  • ADS58B18: 11-Bit, 200MSPS
  • ADS58B19: 9-Bit, 250MSPS
  • Integrated High-Impedance Analog Input Buffer
  • Ultralow Power:
    • Analog Power: 258mW at 200MSPS
    • I/O Power: 69mW (DDR LVDS, low LVDS swing)
  • High Dynamic Performance:
    • ADS58B18: 66dBFS SNR and 81dBc SFDR at 150MHz
    • ADS58B19: 55.7dBFS SNR and 76dBc SFDR at 150MHz
  • Enhanced SNR Using TI-Proprietary SNRBoost Technology (ADS58B18 Only)
    • –77.7dBFS SNR in 20MHz Bandwidth
  • Dynamic Power Scaling with Sample Rate
  • Output Interface:
    • Double Data Rate (DDR) LVDS with Programmable Swing and Strength
      • Standard Swing: 350mV
      • Low Swing: 200mV
      • Default Strength: 100Ω Termination
      • 2x Strength: 50Ω Termination
    • 1.8V Parallel CMOS Interface Also Supported
  • Programmable Gain for SNR/SFDR Trade-Off
  • DC Offset Correction
  • Supports Low Input Clock Amplitude
  • Package: QFN-48 (7mm × 7mm)

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open-in-new Find other High-speed ADCs (>10MSPS)


The ADS58B18/B19 are members of the ultralow power ADS4xxx analog-to-digital converter (ADC) family that features integrated analog buffers and SNRBoost technology. The ADS58B18 and ADS58B19 are 11-bit and 9-bit ADCs with sampling rates up to 200MSPS and 250MSPS, respectively. Innovative design techniques are used to achieve high dynamic performance while consuming extremely low power. The analog input pins have buffers with constant performance and input impedance across a wide frequency range. This architecture makes these parts well-suited for multi-carrier, wide bandwidth communications applications such as PA linearization.

The ADS58B18 uses TI-proprietary SNRBoost technology that can be used to overcome SNR limitation as a result of quantization noise for bandwidths less than Nyquist (fS/2).

Both devices have gain options that can be used to improve SFDR performance at lower full-scale input ranges, especially at very high input frequencies. They also include a dc offset correction loop that can be used to cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled-down power with no loss in performance.

These devices support both double data rate (DDR) low-voltage differential signaling (LVDS) and parallel CMOS digital output interfaces. The low data rate of the DDR LVDS interface (maximum 500Mbps) makes it possible to use low-cost field-programmable gate array (FPGA)-based receivers. They have a low-swing LVDS mode that can be used to further reduce the power consumption. The strength of the LVDS output buffers can also be increased to support 50Ω differential termination.

The ADS58B18/B19 are both available in a compact QFN-48 package and specified over the industrial temperature range (–40°C to +85°C).

open-in-new Find other High-speed ADCs (>10MSPS)

Technical documentation

= Featured
No results found. Please clear your search and try again. View all 17
Type Title Date
* Datasheet 11-Bit, 200MSPS/9-Bit, 250MSPS, Ultralow-Power ADCs with Analog Buffer datasheet (Rev. D) Jan. 28, 2011
Technical articles How to achieve fast frequency hopping Mar. 03, 2019
Technical articles RF sampling: Learning more about latency Feb. 09, 2017
Technical articles Why phase noise matters in RF sampling converters Nov. 28, 2016
Technical articles How to minimize filter loss when you drive an ADC Oct. 20, 2016
User guides Interfacing Altera FPGAs to ADS4249 and DAC3482 (TIDA-00069 Reference Guide) Jul. 10, 2012
User guides ADS41xx/58B18EVM User's Guide.. (Rev. C) May 15, 2012
Application notes High-Speed, Analog-to-Digital Converter Basics Jan. 11, 2012
Application notes Power Supply Design for the ADS41xx (Rev. A) Dec. 29, 2011
More literature TI and Altera Ease Design Process with Compatible Evaluation Tools Apr. 25, 2011
More literature TI and Xilinx Ease Design Process with Compatible Evaluation Tools Apr. 25, 2011
Application notes Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) Sep. 10, 2010
Application notes Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio Apr. 28, 2009
Application notes CDCE62005 as Clock Solution for High-Speed ADCs Sep. 04, 2008
Application notes CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters Jun. 08, 2008
Application notes Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 Jun. 02, 2008
Application notes QFN Layout Guidelines Jul. 28, 2006

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

document-generic User guide

The ADS58B18EVM is a circuit board that allows designers to evaluate the performance of Texas Instruments‘ ADS58B18 device, an extremely low power 11-bit 200 MSPS analog to digital converter. The ADC features a buffered analog input and configurable parallel DDR LVDS or CMOS outputs. The EVM (...)

  • Transformer coupled analog input path
  • Amplifier path based on the THS4509
  • Configurable CMOS or DDR LVDS parallel output modes
  • Transformer coupled clock input path
  • CDCE72010 Jitter Clock Synchronizer and Jitter Cleaner clocking circuit
  • DDR LVDS output and capture ability via TSW1200 capture card
  • Separate (...)
    SLAC384B.ZIP (82933 KB)

    Software development

    High-speed data converter pro software
    DATACONVERTERPRO-SW This high-speed data converter pro GUI is a PC (Windows® XP/7 compatible) program designed to aid in evaluation of most TI high-speed data converter and analog front-end (AFE) platforms. Designed to support the entire TSW14xxx series of data-capture and pattern-generation cards (...)
    • Compatible with TSW1400, TSW1405, TSW1406 and TSW14J10, TSW14J50, TSW14J56, and TSW14J57 pattern-generation and data-capture platforms
    • Works with all TI high-speed DAC, ADC, and AFE products
    • Provides time-domain and frequency-domain analysis
    • Supports single-tone, multi-tone, and modulated (...)

    Design tools & simulation

    SBAM091.ZIP (318 KB) - IBIS Model
    SBAM091A.ZIP (318 KB) - IBIS Model
    Jitter and SNR Calculator for ADCs
    JITTER-SNR-CALC JITTER-SNR-CALC can be used for calculating theoretical Signal to Noise (SNR) performance of ADCs based on input frequency and clock jitter.
    SLAR048.ZIP (2222 KB)

    CAD/CAE symbols

    Package Pins Download
    VQFN (RGZ) 48 View options

    Ordering & quality

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