DAC5681Z

ACTIVE

16-Bit, 1.0-GSPS, 1x-4x Interpolating Digital-to-Analog Converter (DAC)

Top

Product details

Parameters

Resolution (Bits) 16 DAC channels 1 Interface Parallel LVDS Sample/update rate (MSPS) 1000 Features Ultra High Speed Rating Catalog Interpolation 1x, 2x, 4x Power consumption (Typ) (mW) 800 SFDR (dB) 81 Architecture Current Sink Operating temperature range (C) -40 to 85 Reference: type Int open-in-new Find other High-speed DACs (>10MSPS)

Package | Pins | Size

VQFN (RGC) 64 81 mm² 9 x 9 open-in-new Find other High-speed DACs (>10MSPS)

Features

  • 16-Bit Digital-to-Analog Converter (DAC)
  • 1.0 GSPS Update Rate
  • 16-Bit Wideband Input LVDS Data Bus
    • 8 Sample Input FIFO
  • High Performance
    • 73-dBc ACLR WCDMA TM1 at 180 MHz
  • 2x to 32x Clock Multiplying PLL/VCO
  • 2x or 4x Interpolation Filters
    • Stopband Transition 0.4–0.6 Fdata
    • Filters Configurable in Either Low-Pass or
      High-Pass Mode
      • Allows Selection of Higher Order Image
  • On-Chip 1.2-V Reference
  • 2 to 20-mA Differential Scalable Output
  • 64-Pin 9-mm × 9-mm VQFN Package
  • APPLICATIONS
    • Cellular Base Stations
    • Broadband Wireless Access (BWA)
    • WiMAX 802.16
    • Fixed Wireless Backhaul
    • Cable Modem Termination System (CMTS)

All other trademarks are the property of their respective owners

open-in-new Find other High-speed DACs (>10MSPS)

Description

The DAC5681Z is a 16-bit 1.0 GSPS digital-to-analog converter (DAC) with wideband LVDS data input, integrated 2x to 4x interpolation filters, on-board clock multiplier, and internal voltage reference. The DAC5681Z offers superior linearity, noise, crosstalk, and PLL phase noise performance.

The DAC5681Z integrates a wideband LVDS port with on-chip termination. Full-rate input data can be transferred to a single DAC channel, or half-rate and 1/4-rate input data can be interpolated by on-board 2x or 4x FIR filters. Each interpolation FIR is configurable in either low-pass or high-pass mode, allowing selection of a higher order output spectral image. An on-chip delay lock loop (DLL) simplifies LVDS interfacing by providing skew control for the LVDS input data clock.

The DAC5681Z is characterized for operation over the industrial temperature range of –40°C to 85°C and is available in a 64-pin VQFN package. Other members of the family include the dual-channel, interpolating DAC5682Z and the single-channel, non-interpolating DAC5681.

open-in-new Find other High-speed DACs (>10MSPS)
Download

Technical documentation

= Featured
No results found. Please clear your search and try again. View all 12
Type Title Date
* Datasheet 16-BIT, 1.0 GSPS 2x-4x INTERPOLATING DAC. datasheet (Rev. G) Dec. 03, 2015
Technical articles Digital signal processing in RF sampling DACs – part 2 Apr. 04, 2017
Technical articles Digital signal processing in RF sampling DACs - part 1 Feb. 13, 2017
Technical articles Why phase noise matters in RF sampling converters Nov. 28, 2016
Technical articles RF sampling: frequency planning yields a clean spectrum Nov. 18, 2015
Application notes High Speed, Digital-to-Analog Converters Basics (Rev. A) Oct. 23, 2012
User guides TSW1400 Pattern Generators May 03, 2012
More literature TI and Altera Ease Design Process with Compatible Evaluation Tools Apr. 25, 2011
More literature TI and Xilinx Ease Design Process with Compatible Evaluation Tools Apr. 25, 2011
Application notes Passive Terminations for Current Output DACs Nov. 10, 2008
Application notes CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters Jun. 08, 2008
Application notes Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 Jun. 02, 2008

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
$499.00
Description
The DAC5681EVM is a circuit board that allows designers to evaluate the performance of Texas Instruments' single-channel 16-bit 1.0 GSPS digital-to-analog converter (DAC) featuring a fll 1GSPS DDR LVDS interface. The EVM provides a flexible environment to test the DAC5681 under a variety of clock (...)
Features
Comprehensive test capability for DAC5681 Direct connection to TSW3100 signal generator EVM Programmable Low Jitter Clock Synthesizer capable of working with a VCXO or an external clock source Clock synchronization with TSW3100 for signal integrity Software support with a fully featured GUI for easy (...)
EVALUATION BOARDS Download
document-generic User guide
Description

The DAC5681ZEVM is a circuit board that allows designers to evaluate the performance of Texas Instruments' single-channel 16-bit 1.0 GSPS digital-to-analog converter (DAC) featuring a fll 1GSPS DDR LVDS interface, integrated 2x/4x interpolation filters, on-board clock multiplier and internal voltage (...)

Features
  • Comprehensive test capability for DAC5681Z
  • Direct connection to TSW3100 signal generator EVM
  • Has a programmable Low Jitter Clock Synthesizer capable of working with a VCXO or an external clock source
  • Clock synchronization with TSW3100 for signal integrity
  • Software support with a fully featured GUI for (...)
EVALUATION BOARDS Download
Abaco Systems® FMC204 FPGA mezzanine card
Provided by Abaco Systems
Description
The FMC204 is a quad channel D/A FMC daughter card. The card is based on TI's DAC5681Z dual channel 16-bit 1 Gsps device. The FMC204 daughter card is mechanically and electrically compliant to FMC standard (ANSI/VITA 57.1). The FMC204 has a high-pin count connector, front panel I/O, and can be used (...)
GUIS FOR EVALUATION MODULES (EVM) Download
SLAC497A.ZIP (59041 KB)
GUIS FOR EVALUATION MODULES (EVM) Download
SLLC420B.ZIP (199990 KB)
GUIS FOR EVALUATION MODULES (EVM) Download
Description
The FMC110 is a dual channel A/D and dual channel D/A FMC daughter card. The card is based on TI's ADS5400 dual channel 12-bit 1 Gsps ADC and TI's DAC5681Z dual channel 16-bit 1 Gsps device. The FMC150 daughter card is mechanically and electrically compliant to FMC standard (ANSI/VITA 57.1). The (...)
INTERFACE ADAPTERS Download
$49.00
Description
The FMC-DAC-Adapter passive interconnect board enables the output of TI’s LVDS input high speed DACs to be directly connected to a standard FMC interconnect header, a typical input on the latest Xilinx FPGA EVMs. This enables users of TI’s high speed DAC EVMs to directly interface to Xilinx (...)
Features
  • Enables direct connection to TI high speed DAC EVM LVDS inputs from the FMC standard header

Software development

SUPPORT SOFTWARE Download
High-speed data converter pro software
DATACONVERTERPRO-SW This high-speed data converter pro GUI is a PC (Windows® XP/7 compatible) program designed to aid in evaluation of most TI high-speed data converter and analog front-end (AFE) platforms. Designed to support the entire TSW14xxx series of data-capture and pattern-generation cards (...)
Features
  • Compatible with TSW1400, TSW1405, TSW1406 and TSW14J10, TSW14J50, TSW14J56, and TSW14J57 pattern-generation and data-capture platforms
  • Works with all TI high-speed DAC, ADC, and AFE products
  • Provides time-domain and frequency-domain analysis
  • Supports single-tone, multi-tone, and modulated (...)

Design tools & simulation

SIMULATION MODELS Download
SLLC320A.ZIP (7 KB) - IBIS Model
CALCULATION TOOLS Download
SLAC169.ZIP (33 KB)

CAD/CAE symbols

Package Pins Download
VQFN (RGC) 64 View options

Ordering & quality

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos

Related videos