Product details

Resolution (Bits) 16 Number of DAC channels (#) 1 Interface type Parallel LVDS Sample/update rate (MSPS) 1000 Features Ultra High Speed Rating Catalog Interpolation 1x, 2x, 4x Power consumption (Typ) (mW) 800 SFDR (dB) 81 Architecture Current Sink Operating temperature range (C) -40 to 85 Reference type Int
Resolution (Bits) 16 Number of DAC channels (#) 1 Interface type Parallel LVDS Sample/update rate (MSPS) 1000 Features Ultra High Speed Rating Catalog Interpolation 1x, 2x, 4x Power consumption (Typ) (mW) 800 SFDR (dB) 81 Architecture Current Sink Operating temperature range (C) -40 to 85 Reference type Int
VQFN (RGC) 64 81 mm² 9 x 9
  • 16-Bit Digital-to-Analog Converter (DAC)
  • 1.0 GSPS Update Rate
  • 16-Bit Wideband Input LVDS Data Bus
    • 8 Sample Input FIFO
  • High Performance
    • 73-dBc ACLR WCDMA TM1 at 180 MHz
  • 2x to 32x Clock Multiplying PLL/VCO
  • 2x or 4x Interpolation Filters
    • Stopband Transition 0.4–0.6 Fdata
    • Filters Configurable in Either Low-Pass or
      High-Pass Mode
      • Allows Selection of Higher Order Image
  • On-Chip 1.2-V Reference
  • 2 to 20-mA Differential Scalable Output
  • 64-Pin 9-mm × 9-mm VQFN Package
  • APPLICATIONS
    • Cellular Base Stations
    • Broadband Wireless Access (BWA)
    • WiMAX 802.16
    • Fixed Wireless Backhaul
    • Cable Modem Termination System (CMTS)

All other trademarks are the property of their respective owners

  • 16-Bit Digital-to-Analog Converter (DAC)
  • 1.0 GSPS Update Rate
  • 16-Bit Wideband Input LVDS Data Bus
    • 8 Sample Input FIFO
  • High Performance
    • 73-dBc ACLR WCDMA TM1 at 180 MHz
  • 2x to 32x Clock Multiplying PLL/VCO
  • 2x or 4x Interpolation Filters
    • Stopband Transition 0.4–0.6 Fdata
    • Filters Configurable in Either Low-Pass or
      High-Pass Mode
      • Allows Selection of Higher Order Image
  • On-Chip 1.2-V Reference
  • 2 to 20-mA Differential Scalable Output
  • 64-Pin 9-mm × 9-mm VQFN Package
  • APPLICATIONS
    • Cellular Base Stations
    • Broadband Wireless Access (BWA)
    • WiMAX 802.16
    • Fixed Wireless Backhaul
    • Cable Modem Termination System (CMTS)

All other trademarks are the property of their respective owners

The DAC5681Z is a 16-bit 1.0 GSPS digital-to-analog converter (DAC) with wideband LVDS data input, integrated 2x to 4x interpolation filters, on-board clock multiplier, and internal voltage reference. The DAC5681Z offers superior linearity, noise, crosstalk, and PLL phase noise performance.

The DAC5681Z integrates a wideband LVDS port with on-chip termination. Full-rate input data can be transferred to a single DAC channel, or half-rate and 1/4-rate input data can be interpolated by on-board 2x or 4x FIR filters. Each interpolation FIR is configurable in either low-pass or high-pass mode, allowing selection of a higher order output spectral image. An on-chip delay lock loop (DLL) simplifies LVDS interfacing by providing skew control for the LVDS input data clock.

The DAC5681Z is characterized for operation over the industrial temperature range of –40°C to 85°C and is available in a 64-pin VQFN package. Other members of the family include the dual-channel, interpolating DAC5682Z and the single-channel, non-interpolating DAC5681.

The DAC5681Z is a 16-bit 1.0 GSPS digital-to-analog converter (DAC) with wideband LVDS data input, integrated 2x to 4x interpolation filters, on-board clock multiplier, and internal voltage reference. The DAC5681Z offers superior linearity, noise, crosstalk, and PLL phase noise performance.

The DAC5681Z integrates a wideband LVDS port with on-chip termination. Full-rate input data can be transferred to a single DAC channel, or half-rate and 1/4-rate input data can be interpolated by on-board 2x or 4x FIR filters. Each interpolation FIR is configurable in either low-pass or high-pass mode, allowing selection of a higher order output spectral image. An on-chip delay lock loop (DLL) simplifies LVDS interfacing by providing skew control for the LVDS input data clock.

The DAC5681Z is characterized for operation over the industrial temperature range of –40°C to 85°C and is available in a 64-pin VQFN package. Other members of the family include the dual-channel, interpolating DAC5682Z and the single-channel, non-interpolating DAC5681.

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Technical documentation

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Type Title Date
* Data sheet 16-BIT, 1.0 GSPS 2x-4x INTERPOLATING DAC. datasheet (Rev. G) 03 Dec 2015
Application note High Speed, Digital-to-Analog Converters Basics (Rev. A) 23 Oct 2012
User guide TSW1400 Pattern Generators 03 May 2012
More literature TI and Altera Ease Design Process with Compatible Evaluation Tools 25 Apr 2011
More literature TI and Xilinx Ease Design Process with Compatible Evaluation Tools 25 Apr 2011
Application note Passive Terminations for Current Output DACs 10 Nov 2008
Application note CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters 08 Jun 2008
Application note Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 02 Jun 2008

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

DAC5681ZEVM — DAC5681Z 16-Bit, 1.0-GSPS, 1x-4x Interpolating Digital-to-Analog Converter Evaluation Module

The DAC5681ZEVM is a circuit board that allows designers to evaluate the performance of Texas Instruments' single-channel 16-bit 1.0 GSPS digital-to-analog converter (DAC) featuring a fll 1GSPS DDR LVDS interface, integrated 2x/4x interpolation filters, on-board clock multiplier and internal (...)

User guide: PDF
Not available on TI.com
Evaluation board

ABACO-3P-FMC204FPGA — Abaco Systems® FMC204 FPGA mezzanine card

The FMC204 is a quad channel D/A FMC daughter card. The card is based on TI's DAC5681Z dual channel 16-bit 1 Gsps device. The FMC204 daughter card is mechanically and electrically compliant to FMC standard (ANSI/VITA 57.1). The FMC204 has a high-pin count connector, front panel I/O, and can be (...)
Daughter card

ABACO-3P-FMC110FPGA — Abaco Systems® FMC110 FPGA mezzanine card

The FMC110 is a dual channel A/D and dual channel D/A FMC daughter card. The card is based on TI's ADS5400 dual channel 12-bit 1 Gsps ADC and TI's DAC5681Z dual channel 16-bit 1 Gsps device. The FMC150 daughter card is mechanically and electrically compliant to FMC standard (ANSI/VITA 57.1). The (...)
Interface adapter

FMC-DAC-ADAPTER — High Speed DAC to FMC (Xilinx) Header Adapter Card

The FMC-DAC-Adapter passive interconnect board enables the output of TI’s LVDS input high speed DACs to be directly connected to a standard FMC interconnect header, a typical input on the latest Xilinx FPGA EVMs. This enables users of TI’s high speed DAC EVMs to directly interface to Xilinx FPGA’s (...)
Not available on TI.com
GUI for evaluation module (EVM)

DAC5682z EVM Software (Rev. A)

SLAC497A.ZIP (59041 KB)
Support software

DATACONVERTERPRO-SW — High-speed data converter pro software

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter and analog front-end (AFE) platforms. Designed to support the entire TSW14xxx series of data-capture and pattern-generation cards, (...)
Simulation model

DAC5681, DAC5681Z, DAC5682Z IBIS Model (Rev. A)

SLLC320A.ZIP (7 KB) - IBIS Model
Calculation tool

DAC5682 LPF Calculator

SLAC169.ZIP (33 KB)
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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VQFN (RGC) 64 View options

Ordering & quality

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