Product details

Sample rate (Max) (MSPS) 105 Resolution (Bits) 14 Number of input channels 2 Interface type DDR LVDS, Parallel CMOS Analog input BW (MHz) 450 Features High Performance Rating Catalog Input range (Vp-p) 2 Power consumption (Typ) (mW) 700 Architecture Pipeline SNR (dB) 74.5 ENOB (Bits) 11.95 SFDR (dB) 92 Operating temperature range (C) -40 to 85 Input buffer No
Sample rate (Max) (MSPS) 105 Resolution (Bits) 14 Number of input channels 2 Interface type DDR LVDS, Parallel CMOS Analog input BW (MHz) 450 Features High Performance Rating Catalog Input range (Vp-p) 2 Power consumption (Typ) (mW) 700 Architecture Pipeline SNR (dB) 74.5 ENOB (Bits) 11.95 SFDR (dB) 92 Operating temperature range (C) -40 to 85 Input buffer No
VQFN (RGC) 64 81 mm² 9 x 9
  • Maximum Sample Rate: 125 MSPS
  • 14-Bit Resolution with No Missing Codes
  • 95 dB Crosstalk
  • Parallel CMOS and DDR LVDS Output Options
  • 3.5 dB Coarse Gain and Programmable Fine Gain
    up to 6 dB for SNR/SFDR Trade-Off
  • Digital Processing Block with:
    • Offset Correction
    • Fine Gain Correction, in Steps of 0.05 dB
    • Decimation by 2/4/8
    • Built-in and Custom Programmable 24-Tap Low-/High-/
      Band-Pass Filters
  • Supports Sine, LVPECL, LVDS and LVCMOS Clocks and
    Amplitude Down to 400 mVPP
  • Clock Duty Cycle Stabilizer
  • Internal Reference; Supports External Reference also
  • 64-QFN Package (9mm × 9mm)
  • Pin Compatible 12-Bit Family (ADS62P2X)
  • Maximum Sample Rate: 125 MSPS
  • 14-Bit Resolution with No Missing Codes
  • 95 dB Crosstalk
  • Parallel CMOS and DDR LVDS Output Options
  • 3.5 dB Coarse Gain and Programmable Fine Gain
    up to 6 dB for SNR/SFDR Trade-Off
  • Digital Processing Block with:
    • Offset Correction
    • Fine Gain Correction, in Steps of 0.05 dB
    • Decimation by 2/4/8
    • Built-in and Custom Programmable 24-Tap Low-/High-/
      Band-Pass Filters
  • Supports Sine, LVPECL, LVDS and LVCMOS Clocks and
    Amplitude Down to 400 mVPP
  • Clock Duty Cycle Stabilizer
  • Internal Reference; Supports External Reference also
  • 64-QFN Package (9mm × 9mm)
  • Pin Compatible 12-Bit Family (ADS62P2X)

ADS62P4X is a dual channel 14-bit A/D converter family with maximum sample rates up to 125 MSPS. It combines high performance and low power consumption in a compact 64 QFN package. Using an internal sample and hold and low jitter clock buffer, the ADC supports high SNR and high SFDR at high input frequencies. It has coarse and fine gain options that can be used to improve SFDR performance at lower full-scale input ranges.

ADS62P4X includes a digital processing block that consists of several useful and commonly used digital functions such as ADC offset correction, fine gain correction (in steps of 0.05 dB), decimation by 2,4,8 and in-built and custom programmable filters. By default, the digital processing block is bypassed, and its functions are disabled.

Two output interface options exist – parallel CMOS and DDR LVDS (Double Data Rate). ADS62P4X includes internal references while traditional reference pins and associated decoupling capacitors have been eliminated. Nevertheless, the device can also be driven with an external reference. The device is specified over the industrial temperature range (–40°C to 85°C).

ADS62P4X is a dual channel 14-bit A/D converter family with maximum sample rates up to 125 MSPS. It combines high performance and low power consumption in a compact 64 QFN package. Using an internal sample and hold and low jitter clock buffer, the ADC supports high SNR and high SFDR at high input frequencies. It has coarse and fine gain options that can be used to improve SFDR performance at lower full-scale input ranges.

ADS62P4X includes a digital processing block that consists of several useful and commonly used digital functions such as ADC offset correction, fine gain correction (in steps of 0.05 dB), decimation by 2,4,8 and in-built and custom programmable filters. By default, the digital processing block is bypassed, and its functions are disabled.

Two output interface options exist – parallel CMOS and DDR LVDS (Double Data Rate). ADS62P4X includes internal references while traditional reference pins and associated decoupling capacitors have been eliminated. Nevertheless, the device can also be driven with an external reference. The device is specified over the industrial temperature range (–40°C to 85°C).

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Technical documentation

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Type Title Date
* Data sheet DUAL CHANNEL 14-BITS 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS datasheet (Rev. C) 09 Feb 2012
Technical article Keys to quick success using high-speed data converters 13 Oct 2020
Technical article How to achieve fast frequency hopping 03 Mar 2019
Technical article RF sampling: Learning more about latency 09 Feb 2017
Technical article Why phase noise matters in RF sampling converters 28 Nov 2016
Application note Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) 22 May 2015
Application note Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) 19 Jul 2013
User guide TSW4200 Demonstration Kit User's Guide (Rev. C) 31 Oct 2012
User guide Interfacing Altera FPGAs to ADS4249 and DAC3482 (TIDA-00069 Reference Guide) 10 Jul 2012
Application note Band-Pass Filter Design Techniques for High-Speed ADCs 27 Feb 2012
Application note Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) 10 Sep 2010
Application note Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio 28 Apr 2009
User guide ADS62PxxEVM Quick Start Guide (Rev C Board) (Rev. A) 02 Apr 2009
User guide ADS62PXX EVM User's Guide for EVM Rev. C (Rev. A) 23 Feb 2009
Application note CDCE62005 as Clock Solution for High-Speed ADCs 04 Sep 2008
Application note CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters 08 Jun 2008
Application note Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 02 Jun 2008
User guide ADS62PXX EVM User's Guide 21 May 2008
Application note QFN Layout Guidelines 28 Jul 2006

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

ADS62P44EVM — ADS62P44 Dual-Channel, 14-Bit, 105-MSPS Analog-to-Digital Converter Evaluation Module

The ADS62P44 EVM is a circuit board that allows designers to evaluate the performance of Texas Instruments' ADS62P44 device, a dual channel 14-bit 105 MSPS analog to digital converter. The ADC features a user selectable parallel CMOS or DDR LVDS output. Users can use either the TSW1100 (CMOS mode) (...)

Evaluation board

TSW1405EVM — Data converter data capture evaluation module with 8 LVDS lanes up to 1.0 Gbps

The TSW1405EVM is a low cost data capture circuit board used to evaluate some of Texas Instruments’ (TI) most popular high speed analog-to-digital converters (ADC).

 

The TSW1405EVM supports a high speed LVDS bus capable of providing 16-bit samples at 1.0 GSPS. The platform supports a 64k sample (...)

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Software programming tool

HSADC-SPI-UTILITY — High Speed ADC SPI Programming Tool

Support software

DATACONVERTERPRO-SW — High-speed data converter pro software

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter and analog front-end (AFE) platforms. Designed to support the entire TSW14xxx series of data-capture and pattern-generation cards, (...)
Simulation model

ADS62Pxx Family TINA-TI Transient Spice Model

SBAM007.TSM (14 KB) - TINA-TI Spice Model
Simulation model

ADS62Pxx Family TINA-TI Transient Reference Design

SBAM008.ZIP (6 KB) - TINA-TI Reference Design
Simulation model

ADS62Pxx IBIS Model (Rev. A)

SLAC176A.ZIP (921 KB) - IBIS Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Calculation tool

ADC-HARMONIC-CALC — Analog-to-digital converter (ADC) harmonic calculator

    The ADC Harmonic Calculation tool is an excel based calculator for determining the location in frequency space of high order harmonics following Nyquist aliasing in an analog to digital converter.

    Given an ADC sample rate and the span of a signal of interest the calcultor will determine if the 2nd (...)

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VQFN (RGC) 64 View options

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