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Product details

Parameters

Sample rate (Max) (MSPS) 250 Resolution (Bits) 12 Number of input channels 1 Analog input BW (MHz) 800 Features High Performance Rating Catalog Input range (Vp-p) 1.5 Power consumption (Typ) (mW) 350 Architecture Pipeline SNR (dB) 69.7 ENOB (Bits) 11.2 SFDR (dB) 89 Operating temperature range (C) -40 to 85 Input buffer Yes open-in-new Find other High-speed ADCs (>10MSPS)

Package | Pins | Size

VQFN (RGZ) 48 49 mm² 7 x 7 open-in-new Find other High-speed ADCs (>10MSPS)

Features

  • ADS41B49: 14-Bit, 250 MSPS
    ADS41B29: 12-Bit, 250 MSPS
  • Integrated High-Impedance
    Analog Input Buffer:
    • Input Capacitance: 2 pF
    • 200-MHz Input Resistance: 3 kΩ
  • Maximum Sample Rate: 250 MSPS
  • Ultralow Power:
    • 1.8-V Analog Power: 180 mW
    • 3.3-V Buffer Power: 96 mW
    • I/O Power: 135 mW (DDR LVDS)
  • High Dynamic Performance:
    • SNR: 69 dBFS at 170 MHz
    • SFDR: 82.5 dBc at 170 MHz
  • Output Interface:
    • Double Data Rate (DDR) LVDS with Programmable Swing and Strength:
      • Standard Swing: 350 mV
      • Low Swing: 200 mV
      • Default Strength: 100-Ω Termination
      • 2x Strength: 50-Ω Termination
    • 1.8-V Parallel CMOS Interface Also Supported
  • Programmable Gain for SNR, SFDR Trade-Off
  • DC Offset Correction
  • Supports Low Input Clock Amplitude
  • Package: VQFN-48 (7 mm × 7 mm)
open-in-new Find other High-speed ADCs (>10MSPS)

Description

The ADS41Bx9 are members of the ultralow-power ADS4xxx analog-to-digital converter (ADC) family, featuring integrated analog input buffers. These devices use innovative design techniques to achieve high dynamic performance, and consume extremely low power. The analog input pins have buffers, with benefits of constant performance and input impedance across a wide frequency range. The devices are well-suited for multi-carrier, wide bandwidth communications applications such as PA linearization.

The ADS41Bx9 have features such as digital gain and offset correction. The gain option can be used to improve SFDR performance at lower full-scale input ranges, especially at high input frequencies. The integrated dc offset correction loop can be used to estimate and cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled-down power with no loss in performance.

The devices support both double data rate (DDR) low-voltage differential signaling (LVDS) and parallel CMOS digital output interfaces. The low data rate of the DDR LVDS interface (maximum 500 MBPS) makes using low-cost field-programmable gate array (FPGA)-based receivers possible. The devices have a low-swing LVDS mode that can be used to further reduce the power consumption. The strength of the LVDS output buffers can also be increased to support 50-Ω differential termination.

The devices are available in a compact VQFN-48 package and are specified over the industrial temperature range (–40°C to +85°C).

open-in-new Find other High-speed ADCs (>10MSPS)
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Technical documentation

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No results found. Please clear your search and try again. View all 16
Type Title Date
* Datasheet ADS41Bx9 14- and 12-Bit, 250-MSPS, Ultralow-Power ADCs with Analog Buffers datasheet (Rev. F) Feb. 11, 2016
Technical articles How to achieve fast frequency hopping Mar. 03, 2019
Technical articles RF sampling: Learning more about latency Feb. 09, 2017
Technical articles Why phase noise matters in RF sampling converters Nov. 28, 2016
Technical articles How to minimize filter loss when you drive an ADC Oct. 20, 2016
Application notes Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) May 22, 2015
Application notes Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) Jul. 19, 2013
User guides Interfacing Altera FPGAs to ADS4249 and DAC3482 (TIDA-00069 Reference Guide) Jul. 10, 2012
User guides ADS41xx/58B18EVM User's Guide.. (Rev. C) May 15, 2012
Application notes Band-Pass Filter Design Techniques for High-Speed ADCs Feb. 27, 2012
Application notes High-Speed, Analog-to-Digital Converter Basics Jan. 11, 2012
Application notes Power Supply Design for the ADS41xx (Rev. A) Dec. 29, 2011
Application notes CDCE62005 as Clock Solution for High-Speed ADCs Sep. 04, 2008
Application notes CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters Jun. 08, 2008
Application notes Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 Jun. 02, 2008
Application notes QFN Layout Guidelines Jul. 28, 2006

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
Description

The ADS4149EVM is a circuit board that allows designers to evaluate the performance of Texas Instruments‘ ADS4149 device, an extremely low power 14-bit 250 MSPS analog to digital converter. The ADC features a configurable parallel DDR LVDS or CMOS outputs. The EVM provides a flexible (...)

Features
  • Transformer coupled analog input path
  • Amplifier path based on the THS4509
  • Configurable CMOS or DDR LVDS parallel output modes
  • Transformer coupled clock input path
  • CDCE72010 Jitter Clock Synchronizer and Jitter Cleaner clocking circuit
  • DDR LVDS output and capture ability via TSW1400EVM or TSW1405EVM (...)
EVALUATION BOARDS Download
document-generic User guide
$299.00
Description

The ADS41B29EVM is a circuit board that allows designers to evaluate the performance of Texas Instruments‘ ADS41B29 device, an extremely low power 12-bit 250 MSPS analog to digital converter with integrated high-impedance input buffer. The ADC features a configurable parallel DDR LVDS or CMOS (...)

Features
  • Transformer coupled analog input path
  • Amplifier path based on the THS4509
  • Configurable CMOS or DDR LVDS parallel output modes
  • Transformer coupled clock input path
  • CDCE72010 Jitter Clock Synchronizer and Jitter Cleaner clocking circuit
  • DDR LVDS output and capture ability via TSW1400EVM or TSW1405EVM (...)
  • EVALUATION BOARDS Download
    document-generic User guide
    $99.00
    Description

    The TSW1405EVM is a low cost data capture circuit board used to evaluate some of Texas Instruments’ (TI) most popular high speed analog-to-digital converters (ADC).

     

    The TSW1405EVM supports a high speed LVDS bus capable of providing 16-bit samples at 1.0 GSPS. The platform supports a 64k sample depth (...)

    Features
  • Simple 16-bit waveform capture from many of TI’s high speed ADC EVM’s
  • Supports 64k sample depth at up to 1.0 GSPS LVDS I/O rates
  • LatticeECP3 high speed mini FPGA
  • Analyzes up to 8 channels concurrently
  • Single mini USB cable for power and data
  • Utilizes an intuitive/easy-to-use GUI package
  • Industry’s (...)
  • EVALUATION BOARDS Download
    document-generic User guide
    $399.00
    Description

    The TSW3085 Evalutaion Module is a circuit board that allows system designers to evaluate the combined performance of Texas Instruments' transmit signal chain with the LMK04806B (formally National Semiconductor) low noise clock generator/jitter cleaner. For ease of use as a complete RF transmit (...)

    Features
  • Includes LMK04806B for clock generation and jitter cleaning
  • Direct connection to TSW3100 signal generator
  • Comprehensive test capability for the transmitter (DAC3482 dual DAC and TRF3705 IQ Modulator) at analog baseband, IF and RF outputs
  • Software support with a full featured GUI for easy testing and (...)
  • GUIS FOR EVALUATION MODULES (EVM) Download
    SLAC384B.ZIP (82933 KB)

    Software development

    SUPPORT SOFTWARE Download
    High-speed data converter pro software
    DATACONVERTERPRO-SW This high-speed data converter pro GUI is a PC (Windows® XP/7 compatible) program designed to aid in evaluation of most TI high-speed data converter and analog front-end (AFE) platforms. Designed to support the entire TSW14xxx series of data-capture and pattern-generation cards (...)
    Features
    • Compatible with TSW1400, TSW1405, TSW1406 and TSW14J10, TSW14J50, TSW14J56, and TSW14J57 pattern-generation and data-capture platforms
    • Works with all TI high-speed DAC, ADC, and AFE products
    • Provides time-domain and frequency-domain analysis
    • Supports single-tone, multi-tone, and modulated (...)
    SUPPORT SOFTWARE Download
    SBAC120.ZIP (262219 KB)

    Design tools & simulation

    SIMULATION MODELS Download
    SBAM091.ZIP (318 KB) - IBIS Model
    SIMULATION MODELS Download
    SBAM091A.ZIP (318 KB) - IBIS Model
    CALCULATION TOOLS Download
    Jitter and SNR Calculator for ADCs
    JITTER-SNR-CALC JITTER-SNR-CALC can be used for calculating theoretical Signal to Noise (SNR) performance of ADCs based on input frequency and clock jitter.
    DESIGN TOOLS Download
    SBAC119B.ZIP (3547 KB)
    BILL OF MATERIALS (BOM) Download
    SLAR048.ZIP (2222 KB)

    CAD/CAE symbols

    Package Pins Download
    VQFN (RGZ) 48 View options

    Ordering & quality

    Support & training

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