Product details

Sample rate (max) (Msps) 135 Resolution (Bits) 16 Number of input channels 1 Interface type Parallel LVDS Analog input BW (MHz) 485 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 3 Power consumption (typ) (mW) 2100 Architecture Pipeline SNR (dB) 79 ENOB (Bits) 12.6 SFDR (dB) 97 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 135 Resolution (Bits) 16 Number of input channels 1 Interface type Parallel LVDS Analog input BW (MHz) 485 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 3 Power consumption (typ) (mW) 2100 Architecture Pipeline SNR (dB) 79 ENOB (Bits) 12.6 SFDR (dB) 97 Operating temperature range (°C) -40 to 85 Input buffer Yes
VQFN (RGC) 64 81 mm² 9 x 9
  • 80/105/135-MSPS Sample Rates
  • 16-Bit Resolution
  • SFDR: 95 dBc at 70 MHz and 135 MSPS
  • SNR: 78.6 dBFS at 70 MHz and 135 MSPS
  • Efficient DDR LVDS-Compatible Outputs
  • Internal Dither Available
  • Total Power Dissipation: 2.2 W
  • Power-Down Mode: 70 mW
  • On-Chip High Impedance Analog Buffer
  • QFN-64 PowerPAD Package (9 mm × 9 mm Footprint)
  • Industrial Temperature Range: –40°C to +85°C
  • APPLICATIONS
    • Wireless Infrastructure (Multi-Carrier GSM, WCDMA, LTE)
    • Test and Measurement Instrumentation
    • Software-Defined Radio
    • Data Acquisition
    • Power Amplifier Linearization
    • Communication Instrumentation
    • Radar
    • Medical Imaging

All trademarks are the property of their respective owners.

  • 80/105/135-MSPS Sample Rates
  • 16-Bit Resolution
  • SFDR: 95 dBc at 70 MHz and 135 MSPS
  • SNR: 78.6 dBFS at 70 MHz and 135 MSPS
  • Efficient DDR LVDS-Compatible Outputs
  • Internal Dither Available
  • Total Power Dissipation: 2.2 W
  • Power-Down Mode: 70 mW
  • On-Chip High Impedance Analog Buffer
  • QFN-64 PowerPAD Package (9 mm × 9 mm Footprint)
  • Industrial Temperature Range: –40°C to +85°C
  • APPLICATIONS
    • Wireless Infrastructure (Multi-Carrier GSM, WCDMA, LTE)
    • Test and Measurement Instrumentation
    • Software-Defined Radio
    • Data Acquisition
    • Power Amplifier Linearization
    • Communication Instrumentation
    • Radar
    • Medical Imaging

All trademarks are the property of their respective owners.

The ADS5481/ADS5482/ADS5483 (ADS548x) is a 16-bit family of analog-to-digital converters (ADCs) that operate from both a 5-V supply and 3.3-V supply while providing LVDS-compatible digital outputs. The ADS548x integrated analog input buffer isolates the internal switching of the onboard track and hold (T&H) from disturbing the signal source while providing a high-impedance input. An internal reference generator is also provided to simplify the system design.

Designed for highest total ENOB, the ADS548x family has outstanding low noise performance and spurious-free dynamic range.

The ADS548x is available in an QFN-64 PowerPAD package. The device is built on Texas Instruments complementary bipolar process (BiCom3) and is specified over the full industrial temperature range (–40°C to +85°C).

The ADS5481/ADS5482/ADS5483 (ADS548x) is a 16-bit family of analog-to-digital converters (ADCs) that operate from both a 5-V supply and 3.3-V supply while providing LVDS-compatible digital outputs. The ADS548x integrated analog input buffer isolates the internal switching of the onboard track and hold (T&H) from disturbing the signal source while providing a high-impedance input. An internal reference generator is also provided to simplify the system design.

Designed for highest total ENOB, the ADS548x family has outstanding low noise performance and spurious-free dynamic range.

The ADS548x is available in an QFN-64 PowerPAD package. The device is built on Texas Instruments complementary bipolar process (BiCom3) and is specified over the full industrial temperature range (–40°C to +85°C).

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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet 16-Bit, 80/105/135 MSPS High-Speed ADCs datasheet (Rev. C) 06 Oct 2009
Analog Design Journal Q3 2009 Issue Analog Applications Journal 24 Sep 2018
Application note Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) 22 May 2015
Analog Design Journal Power-supply design for high-speed ADCs (Rev. A) 18 May 2015
Application note Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) 19 Jul 2013
Application note High-Speed, Analog-to-Digital Converter Basics 11 Jan 2012
Analog Design Journal 3Q 2011 Issue Analog Applications Journal 16 Sep 2011
Application note Clock jitter analyzed in the time domain, Part 3 16 Sep 2011
Application note Input Impedance Measurement Using ADC FFT Data 11 Jan 2011
Analog Design Journal 4Q 2010 Issue Analog Applications Journal 15 Nov 2010
Analog Design Journal Clock jitter analyzed in the time domain, Part 2 15 Nov 2010
Application note Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) 10 Sep 2010
Analog Design Journal Impact of sampling-clock spurs on ADC performance 14 Jul 2009
Application note Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio 28 Apr 2009
Application note CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters 08 Jun 2008
Application note Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 02 Jun 2008
Application note QFN Layout Guidelines 28 Jul 2006

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

GUI for evaluation module (EVM)

DATACONVERTERPRO-SW High Speed Data Converter Pro GUI Installer, v5.31

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)

Supported products & hardware

Supported products & hardware

Simulation model

ADS5483 IBIS Model (Rev. A)

SLAC212A.ZIP (6 KB) - IBIS Model
Calculation tool

ADC-HARMONIC-CALC ADC Frequency Calculator Download

    The ADC Harmonic Calculation tool is an excel based calculator for determining the location in frequency space of high order harmonics following Nyquist aliasing in an analog to digital converter.

    Given an ADC sample rate and the span of a signal of interest the calcultor will determine if the 2nd (...)

Supported products & hardware

Supported products & hardware

Calculation tool

ANALOG-ENGINEER-CALC PC software analog engineer's calculator

The analog engineer’s calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting operational-amplifier (...)

Supported products & hardware

Supported products & hardware

Calculation tool

JITTER-SNR-CALC Jitter and SNR calculator

JITTER-SNR-CALC can be used for calculating theoretical Signal to Noise (SNR) performance of ADCs based on input frequency and clock jitter.

Supported products & hardware

Supported products & hardware

Design tool

SBAC119 TIGAR (Texas Instruments Graphical Evaluation of ADC Response Tool)

Supported products & hardware

Supported products & hardware

Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Package Pins CAD symbols, footprints & 3D models
VQFN (RGC) 64 Ultra Librarian

Ordering & quality

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