ADC08200 8-Bit 200MSPS Low-Power Analog-to-Digital Converter (ADC) With Internal Sample and Hold | TI.com

ADC08200 (ACTIVE)

8-Bit 200MSPS Low-Power Analog-to-Digital Converter (ADC) With Internal Sample and Hold

 

Description

The ADC08200 is a low-power, 8-bit, monolithic analog-to-digital converter with an on-chip track-and-hold circuit. Optimized for low cost, low power, small size and ease of use, this product operates at conversion rates up to 230 Msps while consuming just 1.05 mW per MHz of clock frequency, or 210 mW at 200 Msps. Raising the PD pin puts the ADC08200 into a Power Down mode where it consumes about 1 mW.

The unique architecture achieves 7.3 Effective Bits with 50 MHz input frequency. The ADC08200 is resistant to latch-up and the outputs are short-circuit proof. The top and bottom of the ADC08200's reference ladder are available for connections, enabling a wide range of input possibilities. The digital outputs are TTL/CMOS compatible with a separate output power supply pin to support interfacing with 3V or 2.5V logic. The digital inputs (CLK and PD) are TTL/CMOS compatible. The output data format is straight binary.

The ADC08200 is offered in a 24-lead TSSOP package and, while specified over the industrial temperature range of −40°C to +85°C, it will function over the to −40°C to +105°C temperature range.

Features

  • Single-Ended Input
  • Internal Sample-and-Hold Function
  • Low Voltage (Single +3V) Operation
  • Small Package
  • Power-Down Feature

Key Specifications

  • Resolution 8 Bits
  • Maximum sampling frequency 200 Msps (min)
  • DNL ±0.4 LSB (typ)
  • ENOB (fIN = 50 MHz) 7.3 bits (typ)
  • THD (fIN = 50 MHz) 61 dB (typ)
  • Power Consumption
    • Operating 1.05 mW/Msps (typ)
    • Power Down 1 mW (typ)

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Parametrics Compare all products in High-speed ADCs (>10MSPS)

 
Sample Rate (Max) (MSPS)
Features
Resolution (Bits)
Number of input channels
SNR (dB)
ENOB (Bits)
SFDR (dB)
Power consumption (Typ) (mW)
Input range (Vp-p)
Interface
Operating temperature range (C)
Analog input BW (MHz)
Input buffer
Package Group
Package size: mm2:W x L (PKG)
Rating
Architecture
DNL (Typ) (+/-LSB)
INL (Typ) (+/-LSB)
Reference mode
ADC08200 ADC08060 ADC08100 ADC08L060
200     60     100     60    
Low Power     Low Power     Low Power     Low Power    
8     8     8     8    
1     1     1     1    
46     47     47     48    
7.3     7.1     7.5     7.6    
60     63     60     59.1    
210     88     126     53    
1.6     1.6     1.6     1.6    
Parallel CMOS
TTL    
Parallel CMOS
TTL    
Parallel CMOS
TTL    
Parallel CMOS
TTL    
-40 to 85     -40 to 85     -40 to 85     -40 to 85    
500     200     200     270    
No     No     No     No    
TSSOP | 24     TSSOP | 24     TSSOP | 24     TSSOP | 24    
24TSSOP: 50 mm2: 6.4 x 7.8 (TSSOP | 24)     24TSSOP: 50 mm2: 6.4 x 7.8 (TSSOP | 24)     24TSSOP: 50 mm2: 6.4 x 7.8 (TSSOP | 24)     24TSSOP: 50 mm2: 6.4 x 7.8 (TSSOP | 24)    
Catalog     Catalog     Catalog     Catalog    
Pipeline     Pipeline     Pipeline     Pipeline    
0.4     0.4     0.4     0.25    
1     0.5     0.5     0.5    
Ext     Ext     Ext     Ext