Product details

Sample rate (Max) (MSPS) 250 Resolution (Bits) 9 Number of input channels 1 Interface type Parallel CMOS, Parallel LVDS Analog input BW (MHz) 550 Features Low Power Rating Catalog Input range (Vp-p) 1.5 Power consumption (Typ) (mW) 287 Architecture Pipeline SNR (dB) 55.8 ENOB (Bits) 9 SFDR (dB) 76.5 Operating temperature range (C) -40 to 85 Input buffer Yes
Sample rate (Max) (MSPS) 250 Resolution (Bits) 9 Number of input channels 1 Interface type Parallel CMOS, Parallel LVDS Analog input BW (MHz) 550 Features Low Power Rating Catalog Input range (Vp-p) 1.5 Power consumption (Typ) (mW) 287 Architecture Pipeline SNR (dB) 55.8 ENOB (Bits) 9 SFDR (dB) 76.5 Operating temperature range (C) -40 to 85 Input buffer Yes
VQFN (RGZ) 48 49 mm² 7 x 7
  • ADS58B18: 11-Bit, 200MSPS
  • ADS58B19: 9-Bit, 250MSPS
  • Integrated High-Impedance Analog Input Buffer
  • Ultralow Power:
    • Analog Power: 258mW at 200MSPS
    • I/O Power: 69mW (DDR LVDS, low LVDS swing)
  • High Dynamic Performance:
    • ADS58B18: 66dBFS SNR and 81dBc SFDR at 150MHz
    • ADS58B19: 55.7dBFS SNR and 76dBc SFDR at 150MHz
  • Enhanced SNR Using TI-Proprietary SNRBoost Technology (ADS58B18 Only)
    • –77.7dBFS SNR in 20MHz Bandwidth
  • Dynamic Power Scaling with Sample Rate
  • Output Interface:
    • Double Data Rate (DDR) LVDS with Programmable Swing and Strength
      • Standard Swing: 350mV
      • Low Swing: 200mV
      • Default Strength: 100Ω Termination
      • 2x Strength: 50Ω Termination
    • 1.8V Parallel CMOS Interface Also Supported
  • Programmable Gain for SNR/SFDR Trade-Off
  • DC Offset Correction
  • Supports Low Input Clock Amplitude
  • Package: QFN-48 (7mm × 7mm)

PowerPAD is a trademark of Texas Instruments Incorporated.
All other trademarks are the property of their respective owners.

  • ADS58B18: 11-Bit, 200MSPS
  • ADS58B19: 9-Bit, 250MSPS
  • Integrated High-Impedance Analog Input Buffer
  • Ultralow Power:
    • Analog Power: 258mW at 200MSPS
    • I/O Power: 69mW (DDR LVDS, low LVDS swing)
  • High Dynamic Performance:
    • ADS58B18: 66dBFS SNR and 81dBc SFDR at 150MHz
    • ADS58B19: 55.7dBFS SNR and 76dBc SFDR at 150MHz
  • Enhanced SNR Using TI-Proprietary SNRBoost Technology (ADS58B18 Only)
    • –77.7dBFS SNR in 20MHz Bandwidth
  • Dynamic Power Scaling with Sample Rate
  • Output Interface:
    • Double Data Rate (DDR) LVDS with Programmable Swing and Strength
      • Standard Swing: 350mV
      • Low Swing: 200mV
      • Default Strength: 100Ω Termination
      • 2x Strength: 50Ω Termination
    • 1.8V Parallel CMOS Interface Also Supported
  • Programmable Gain for SNR/SFDR Trade-Off
  • DC Offset Correction
  • Supports Low Input Clock Amplitude
  • Package: QFN-48 (7mm × 7mm)

PowerPAD is a trademark of Texas Instruments Incorporated.
All other trademarks are the property of their respective owners.

The ADS58B18/B19 are members of the ultralow power ADS4xxx analog-to-digital converter (ADC) family that features integrated analog buffers and SNRBoost technology. The ADS58B18 and ADS58B19 are 11-bit and 9-bit ADCs with sampling rates up to 200MSPS and 250MSPS, respectively. Innovative design techniques are used to achieve high dynamic performance while consuming extremely low power. The analog input pins have buffers with constant performance and input impedance across a wide frequency range. This architecture makes these parts well-suited for multi-carrier, wide bandwidth communications applications such as PA linearization.

The ADS58B18 uses TI-proprietary SNRBoost technology that can be used to overcome SNR limitation as a result of quantization noise for bandwidths less than Nyquist (fS/2).

Both devices have gain options that can be used to improve SFDR performance at lower full-scale input ranges, especially at very high input frequencies. They also include a dc offset correction loop that can be used to cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled-down power with no loss in performance.

These devices support both double data rate (DDR) low-voltage differential signaling (LVDS) and parallel CMOS digital output interfaces. The low data rate of the DDR LVDS interface (maximum 500Mbps) makes it possible to use low-cost field-programmable gate array (FPGA)-based receivers. They have a low-swing LVDS mode that can be used to further reduce the power consumption. The strength of the LVDS output buffers can also be increased to support 50Ω differential termination.

The ADS58B18/B19 are both available in a compact QFN-48 package and specified over the industrial temperature range (–40°C to +85°C).

The ADS58B18/B19 are members of the ultralow power ADS4xxx analog-to-digital converter (ADC) family that features integrated analog buffers and SNRBoost technology. The ADS58B18 and ADS58B19 are 11-bit and 9-bit ADCs with sampling rates up to 200MSPS and 250MSPS, respectively. Innovative design techniques are used to achieve high dynamic performance while consuming extremely low power. The analog input pins have buffers with constant performance and input impedance across a wide frequency range. This architecture makes these parts well-suited for multi-carrier, wide bandwidth communications applications such as PA linearization.

The ADS58B18 uses TI-proprietary SNRBoost technology that can be used to overcome SNR limitation as a result of quantization noise for bandwidths less than Nyquist (fS/2).

Both devices have gain options that can be used to improve SFDR performance at lower full-scale input ranges, especially at very high input frequencies. They also include a dc offset correction loop that can be used to cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled-down power with no loss in performance.

These devices support both double data rate (DDR) low-voltage differential signaling (LVDS) and parallel CMOS digital output interfaces. The low data rate of the DDR LVDS interface (maximum 500Mbps) makes it possible to use low-cost field-programmable gate array (FPGA)-based receivers. They have a low-swing LVDS mode that can be used to further reduce the power consumption. The strength of the LVDS output buffers can also be increased to support 50Ω differential termination.

The ADS58B18/B19 are both available in a compact QFN-48 package and specified over the industrial temperature range (–40°C to +85°C).

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Technical documentation

Design & development

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Evaluation board

ADS58B19EVM — ADS58B19 9-Bit, 250-MSPS Analog-to-Digital Converter Evaluation Module

The ADS58B19EVM is a circuit board that allows designers to evaluate the performance of Texas Instruments‘ ADS58B19EVM device, an extremely low power 9-bit 250 MSPS analog to digital converter. The ADC features a buffered analog input and configurable parallel DDR LVDS or CMOS outputs. The EVM (...)

Not available on TI.com
Evaluation board

TSW3085EVM — Wideband Transmit Signal Chain Evaluation Board and Reference Design

The TSW3085 Evalutaion Module is a circuit board that allows system designers to evaluate the combined performance of Texas Instruments' transmit signal chain with the LMK04806B (formally National Semiconductor) low noise clock generator/jitter cleaner. For ease of use as a complete RF transmit (...)

Not available on TI.com
GUI for evaluation module (EVM)

ADS41xx SPI GUI rev1.6 (Rev. B)

SLAC384B.ZIP (82933 KB)
Support software

DATACONVERTERPRO-SW — High-speed data converter pro software

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter and analog front-end (AFE) platforms. Designed to support the entire TSW14xxx series of data-capture and pattern-generation cards, (...)
Simulation model

ADS414x, ADS412x, ADS58B1x, IBIS MODEL ADS414x, ADS412x, ADS58B1x, IBIS MODEL

Simulation model

ADS414x, ADS412x, ADS58B1x, IBIS MODEL (Rev. A) ADS414x, ADS412x, ADS58B1x, IBIS MODEL (Rev. A)

Simulation tool

PSPICE-FOR-TI PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Bill of materials (BOM)

ADS41xx EVM BOM, Schematic, and PCB ADS41xx EVM BOM, Schematic, and PCB

Package Pins Download
VQFN (RGZ) 48 View options

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