The ADS6445/ADS6444 is a high performance 14 bit 125/105 MSPS quad channel A-D
converter. Serial LVDS data outputs reduce the number of interface lines, resulting in a compact
64-pin QFN package (9 mm × 9 mm) that allows for high system integration density. The device
includes 3.5 dB coarse gain option that can be used to improve SFDR performance with little
degradation in SNR. In addition to the coarse gain, fine gain options also exist, programmable in 1
dB steps up to 6 dB.
The output interface is 2-wire, where each ADC data is serialized and output over two
LVDS pairs. This makes it possible to halve the serial data rate (compared to a 1-wire interface)
and restrict it to less than 1 Gbps easing receiver design. The ADS644X also includes the
traditional 1-wire interface that can be used at lower sampling frequencies.
An internal phase lock loop (PLL) multiplies the incoming ADC sampling clock to derive
the bit clock. The bit clock is used to serialize the 14 bit data from each channel. In addition to
the serial data streams, the frame and bit clocks also are transmitted as LVDS outputs.
The LVDS output buffers have features such as programmable LVDS currents, current
doubling modes and internal termination options. These can be used to widen eye openings and
improve signal integrity, easing capture by the receiver.
The ADC channel outputs can be transmitted either as MSB or LSB first and 2s complement
or straight binary.
The ADS644X has internal references, but also can support an external reference mode. The
device is specified over –55°C to 125°C operating junction temperature range.
The ADS6445/ADS6444 is a high performance 14 bit 125/105 MSPS quad channel A-D
converter. Serial LVDS data outputs reduce the number of interface lines, resulting in a compact
64-pin QFN package (9 mm × 9 mm) that allows for high system integration density. The device
includes 3.5 dB coarse gain option that can be used to improve SFDR performance with little
degradation in SNR. In addition to the coarse gain, fine gain options also exist, programmable in 1
dB steps up to 6 dB.
The output interface is 2-wire, where each ADC data is serialized and output over two
LVDS pairs. This makes it possible to halve the serial data rate (compared to a 1-wire interface)
and restrict it to less than 1 Gbps easing receiver design. The ADS644X also includes the
traditional 1-wire interface that can be used at lower sampling frequencies.
An internal phase lock loop (PLL) multiplies the incoming ADC sampling clock to derive
the bit clock. The bit clock is used to serialize the 14 bit data from each channel. In addition to
the serial data streams, the frame and bit clocks also are transmitted as LVDS outputs.
The LVDS output buffers have features such as programmable LVDS currents, current
doubling modes and internal termination options. These can be used to widen eye openings and
improve signal integrity, easing capture by the receiver.
The ADC channel outputs can be transmitted either as MSB or LSB first and 2s complement
or straight binary.
The ADS644X has internal references, but also can support an external reference mode. The
device is specified over –55°C to 125°C operating junction temperature range.