Inicio Convertidores de datos Convertidores analógico-digitales (ADC) ADC de alta velocidad (≥ 10 MSPS)
Inicio
Convertidores de datos
Convertidores analógico-digitales (ADC)
ADC de alta velocidad (≥ 10 MSPS)

ADS5292

ACTIVO

Convertidor analógico a digital (ADC) de ocho canales, 12 bits y 80 MSPS

Haga su pedido ahora
Hoja de datos

ADS5292

ACTIVO
Hoja de datos Haga su pedido ahora

Detalles del producto

Sample rate (max) (Msps) 80 Resolution (Bits) 12, 14 Number of input channels 8 Interface type Serial LVDS Analog input BW (MHz) 550 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 376 Architecture Pipeline SNR (dB) 72 ENOB (Bits) 11.3 SFDR (dB) 85 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 80 Resolution (Bits) 12, 14 Number of input channels 8 Interface type Serial LVDS Analog input BW (MHz) 550 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 376 Architecture Pipeline SNR (dB) 72 ENOB (Bits) 11.3 SFDR (dB) 85 Operating temperature range (°C) -40 to 85 Input buffer No
HTQFP (PFP) 80 196 mm² 14 x 14
  • Maximum Sample Rate: 80 MSPS/12-Bit
  • High Signal-to-Noise Ratio
    • 70-dBFS SNR at 5 MHz/80 MSPS
    • 71.5-dBFS SNR at 5 MHz/80 MSPS and Decimation Filter = 2
    • 85-dBc SFDR at 5 MHz/80 MSPS
  • Low Power Consumption
    • 48 mW/CH at 50 MSPS
    • 54 mW/CH at 65 MSPS
    • 66 mW/CH at 80 MSPS (2 LVDS Wire Per Channel)
  • Digital Processing Block
    • Programmable FIR Decimation Filter and Oversampling to Minimize
      Harmonic Interference
    • Programmable IIR High Pass Filter to Minimize DC Offset
    • Programmable Digital Gain: 0 dB to 12 dB
    • 2- or 4-=Channel Averaging
  • Flexible Serialized LVDS Outputs:
    • One or Two wires of LVDS Output Lines per Channel Depending on ADC
      Sampling Rate
    • Programmable Mapping Between ADC Input Channels and LVDS Output
      Pins-Eases Board Design
    • Variety of Test Patterns to Verify Data Capture by
      FPGA/Receiver
  • Internal and External References
  • 1.8V Operation for Low Power Consumption
  • Low-Frequency Noise Suppression
  • Recovery From 6-dB Overload within 1 Clock Cycle
  • Package: 12-mm × 12-mm 80-Pin QFP
  • Maximum Sample Rate: 80 MSPS/12-Bit
  • High Signal-to-Noise Ratio
    • 70-dBFS SNR at 5 MHz/80 MSPS
    • 71.5-dBFS SNR at 5 MHz/80 MSPS and Decimation Filter = 2
    • 85-dBc SFDR at 5 MHz/80 MSPS
  • Low Power Consumption
    • 48 mW/CH at 50 MSPS
    • 54 mW/CH at 65 MSPS
    • 66 mW/CH at 80 MSPS (2 LVDS Wire Per Channel)
  • Digital Processing Block
    • Programmable FIR Decimation Filter and Oversampling to Minimize
      Harmonic Interference
    • Programmable IIR High Pass Filter to Minimize DC Offset
    • Programmable Digital Gain: 0 dB to 12 dB
    • 2- or 4-=Channel Averaging
  • Flexible Serialized LVDS Outputs:
    • One or Two wires of LVDS Output Lines per Channel Depending on ADC
      Sampling Rate
    • Programmable Mapping Between ADC Input Channels and LVDS Output
      Pins-Eases Board Design
    • Variety of Test Patterns to Verify Data Capture by
      FPGA/Receiver
  • Internal and External References
  • 1.8V Operation for Low Power Consumption
  • Low-Frequency Noise Suppression
  • Recovery From 6-dB Overload within 1 Clock Cycle
  • Package: 12-mm × 12-mm 80-Pin QFP

Using CMOS process technology and innovative circuit techniques, the ADS5292 is a low power 80MSPS 8-Channel ADC. Low power consumption, high SNR, low SFDR, and consistent overload recovery allow users to design high performance systems.

The ADS5292 has a digital processing block that integrates several commonly used digital functions for improving system performance. It includes a digital filter module that has built-in decimation filters (with low-pass, high-pass and band-pass characteristics). The decimation rate is also programmable (by 2, by 4, or by 8). This makes it useful for narrow-band applications, where the filters can be used conveniently to improve SNR and knock-off harmonics, while at the same time reducing the output data rate. The device includes an averaging mode where two channels (or even four channels) can be averaged to improve SNR.

Serial LVDS outputs reduce the number of interface lines and enable the highest system integration. The digital data from each channel ADC can be output over one or two wires of LVDS output lines depending on the ADC sampling rate. This 2-wire interface helps keep the serial data rate low, allowing low cost FPGA based receivers to be used even at high sample rate. A unique feature is the programmable mapping module that allows flexible mapping between the input channels and the LVDS output pins. This helps greatly reduce the complexity of LVDS output routing and can potentially result in cheaper system boards by reducing the number of PCB layers.

The device integrates an internal reference trimmed to accurately match across devices. Best performance is expected to be achieved through the internal reference mode. The device can be driven with external references as well.

The device is available in a 12 mm × 12 mm 80-pin QFP. It is specified over a –40°C to 85°C operating temperature range. ADS5292 is completely pin-to-pin and register compatible to ADS5294.

Using CMOS process technology and innovative circuit techniques, the ADS5292 is a low power 80MSPS 8-Channel ADC. Low power consumption, high SNR, low SFDR, and consistent overload recovery allow users to design high performance systems.

The ADS5292 has a digital processing block that integrates several commonly used digital functions for improving system performance. It includes a digital filter module that has built-in decimation filters (with low-pass, high-pass and band-pass characteristics). The decimation rate is also programmable (by 2, by 4, or by 8). This makes it useful for narrow-band applications, where the filters can be used conveniently to improve SNR and knock-off harmonics, while at the same time reducing the output data rate. The device includes an averaging mode where two channels (or even four channels) can be averaged to improve SNR.

Serial LVDS outputs reduce the number of interface lines and enable the highest system integration. The digital data from each channel ADC can be output over one or two wires of LVDS output lines depending on the ADC sampling rate. This 2-wire interface helps keep the serial data rate low, allowing low cost FPGA based receivers to be used even at high sample rate. A unique feature is the programmable mapping module that allows flexible mapping between the input channels and the LVDS output pins. This helps greatly reduce the complexity of LVDS output routing and can potentially result in cheaper system boards by reducing the number of PCB layers.

The device integrates an internal reference trimmed to accurately match across devices. Best performance is expected to be achieved through the internal reference mode. The device can be driven with external references as well.

The device is available in a 12 mm × 12 mm 80-pin QFP. It is specified over a –40°C to 85°C operating temperature range. ADS5292 is completely pin-to-pin and register compatible to ADS5294.

filter Buscar otro/a ADC de alta velocidad (≥ 10 MSPS)
Descargar Ver vídeo con transcripción Video

Documentación técnica

star =Principal documentación para este producto seleccionada por TI
No se encontraron resultados. Borre su búsqueda y vuelva a intentarlo.
Ver todo 4
Documentación principal Tipo Título Opciones de formato Fecha
* Data sheet Octal Channel 12-Bit, 80 MSPS and Low-Power ADC datasheet (Rev. B) 25 jul 2012
Application note Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) 22 may 2015
Application note Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) 19 jul 2013
Application note Understanding Serial LVDS Capture in High-Speed ADCs 10 jul 2013

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

ADS5292EVM — Módulo de evaluación ADS5292

El EVM ADS5292 proporciona un entorno flexible para probar el ADS5292 bajo una variedad de condiciones de reloj y entrada. Este EVM permite a los clientes diseñar sus propios filtros, rellenar el EVM con los componentes correspondientes y verificar el rendimiento en el propio EVM.

Tenga en cuenta (...)

Guía del usuario: PDF
No disponible en TI.com
GUI para el módulo de evaluación (EVM)

SLAC508 — ADS5292EVM GUI Installer

Productos y hardware compatibles

Productos y hardware compatibles
Descargar
Soporte de software

SBAC120 — TIGAR Support Files

Productos y hardware compatibles

Productos y hardware compatibles
Descargar
Modelo de simulación

ADS5294 IBIS Model

SLAM122.ZIP (14 KB) - IBIS Model
Descargar
Herramienta de cálculo

ANALOG-ENGINEER-CALC — PC software analog engineer's calculator

The analog engineer’s calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting operational-amplifier (...)

Productos y hardware compatibles

Productos y hardware compatibles
Iniciar Descargar
Herramienta de diseño

SBAC119 — TIGAR (Texas Instruments Graphical Evaluation of ADC Response Tool)

Productos y hardware compatibles

Productos y hardware compatibles
Descargar
Herramienta de simulación

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

PSpice® para TI es un entorno de diseño y simulación que ayuda a evaluar la funcionalidad de los circuitos analógicos. Esta completa suite de diseño y simulación utiliza un motor de análisis analógico de Cadence®. Disponible sin ningún costo, PSpice para TI incluye una de las bibliotecas de modelos (...)
Solicitar
Encapsulado Pines Símbolos CAD, huellas y modelos 3D
HTQFP (PFP) 80 Ultra Librarian
Se aplican los Términos y condiciones estándar de TI para los elementos de evaluación.

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL)/reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

Los productos recomendados pueden tener parámetros, módulos de evaluación o diseños de referencia relacionados con este producto de TI.

Soporte y capacitación

Foros de TI E2E™ con asistencia técnica de los ingenieros de TI

Ver todos los temas del foro en inglés

El contenido lo proporcionan “tal como está” TI y los colaboradores de la comunidad y no constituye especificaciones de TI. Consulte los términos de uso.

Si tiene alguna pregunta sobre calidad, encapsulados o pedido de productos de TI, consulte el servicio de asistencia de TI. ​​​​​​​​​​​​​​

Videos