SPRUIL1 User guide

SPRUIL1D May 2019 – December 2024 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4VM , TDA4VM-Q1

8.2.2 DDRSS Environment

This section describes the DDRSS0 external connections (environment).

Figure 8-7 shows an example connection to dual rank LPDDR4 x32 device.

Figure 8-7 LPDDR4 Connection

Table 8-13 describes the DDRSS0 I/O signals used for connection to SDRAM devices.

Table 8-13 DDRSS0 I/O signals

Module Pin	Device Level Signal	I/O⁽¹⁾	Description	Module Pin Reset Value⁽²⁾
RSTN	DDR0_RESETn	I/O	SDRAM reset	0x0
CKE[1-0]	DDR0_CKE[1-0]	I/O	SDRAM CKE[1-0] signals	0x0
CK	DDR0_CKP	I/O	SDRAM differential clock pair	0x0
CKN	DDR0_CKN	I/O	SDRAM differential clock pair	0x1
CSN0_0	DDR0_CSn0_0	I/O	SDRAM chip select 0 (two copies of CS0)⁽³⁾	0x0
CSN0_1	DDR0_CSn0_1	I/O	SDRAM chip select 0 (two copies of CS0)⁽³⁾	0x0
CSN1_0	DDR0_CSn1_0	I/O	SDRAM chip select 1 (two copies of CS1)⁽³⁾	0x0
CSN1_1	DDR0_CSn1_1	I/O	SDRAM chip select 1 (two copies of CS1)⁽³⁾	0x0
CA[5-0]	DDR0_CA[5-0]	I/O	SDRAM address and command bus	HiZ
DQS[3-0]	DDR0_DQS[3-0]P	I/O	SDRAM data strobe	HiZ
DQSN[3-0]	DDR0_DQS[3-0]N	I/O	SDRAM data strobe invert	HiZ
DQ[31-0]	DDR0_DQ[31-0]	I/O	SDRAM data bus	HiZ
DM[3-0]	DDR0_DM[3-0]	I/O	SDRAM data mask/DBI	HiZ
RET	DDR_RET	I/O	External I/O retention enable	-

(1) I = Input; O = Output

(2) HiZ = High Impedance

(3) Chip select for each channel is controlled independently during CA training, but they run in locked-step during normal operation.

Note:

For more information about device level signals (pull-up/down resistors, buffer type, multiplexing and others), see tables Pin Attributes and Pin Multiplexing in the device-specific Datasheet.