SPRUIL1 User guide

SPRUIL1D May 2019 – December 2024 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4VM , TDA4VM-Q1

12.7.3.5.9 Clock Lane Control FSMs

The clock lane is controlled in HS and ULP modes using two simple FSMs which have been implemented in the clock control module. Separate FSMs are required as the HS and ULP signals operate in different clock domains.

A brief description of the states of the HS clock lane FSM is presented in Table 12-1544.

Table 12-1544 HS Clock Lane Control FSM State Description

State (clk_fsm_r)	Description
CLK_IDLE	Waiting for HS request and for Clock ULPS FSM to enter IDLE
CLK_HS_REQ	HS mode request, waiting for DPHY_TX HS mode active
CLK_HS_MODE	HS mode active
CLK_HS_EXIT	Exiting HS mode

A brief description of the states of the ULP clock lane FSM is presented in Table 12-1545.

Table 12-1545 ULPS Clock Lane Control FSM State Description

State (clk_fsm_r)	Description
ULPS_CLK_IDLE	Waiting for ULP request and for HS Clock Lane FSM to enter IDLE
ULPS_CLK_ULPS_REQ	ULP state request, waiting for DPHY_TX ULPS state active
ULPS_CLK_ULPS_ACTIVE	ULPS state is active
ULPS_CLK_ULPS_EXIT	Exiting ULPS. Waiting for time defined in DPHY_CLK_WAKEUP register

The clock lane will operate in either continuous or non-continuous clock operation based on the bit value on the CSI_TX_IF_DPHY_CFG[10] DPHY_CLOCK_MODE register bitfield. When the non-continuous clock mode is active the clock lane will automatically move between LP and HS modes based on the activity of the streams.

Figure 12-1173 Clock Lane Control FSMs Timing Diagram

In this mode of operation, after a High Speed burst, if there are no new HS requests pending, the CSI_TX_IF controller will deactivate the Clock Lane request, and the Clock Lane will exit High Speed mode and reach stop state. The Clock Lane will remain in LP while there are no active requests. When a hew HS request is received, the Clock Lane will exit LP mode and resume High Speed operation.

The CSI_TX_IF controller can request that the DPHY_TX enters ULPS when there are no active frames, and must return through LP11 when there are new requests to be processed by changing the CSI_TX_IF_DPHY_CFG[9-8] DPHY_MODE back to High Speed.