Power-on corepac sequence follows this order:
- The processor C66x_DSPSS is off.
- The processor is first powered up by turning on the power switch. At this step, the clock remains off.
- Asynchronous clk_divalign reset is asserted to reset the clocks.
- ASYNC_CLK_DIVALIGN reset is deserted, all clocks will start toggling at the desired frequencies.
- For C66x_DSPSS, the input clock is C66_CLK1_CLK and PLL_CTRL_CLK
- After clock is brought up, POR reset should take place and set debug, PBIST logic in starting state before de-asserted. After POR reset is de-asserted for n cycle which guaranteed the reset took effect, the processor CorePac is powered up, therefore, ISO_ON can be de-asserted.
- Then the processor or core functional logic should be brought to life by de-assert the CLKSTOP_REQ, CLKSTOP_ACK will follow
- Finally, the warm MOD_G_RST is de-asserted a few cycles to start the processor function.
DSP clock, reset and Power management sequencing in detail:
Power-up:
- The processor corepac is off.
- The processor is first powered up by turning on the power switch.
- ASYNC_CLK_DIVALIGN reset is deserted, all clocks will start toggling at the desired frequencies.
- CLK_EN should be asserted for a few cycles then deasserted while the corepac is still in reset to bring everything to reset values (acknowledge will follow).
- After clocks have been brought up, POR_RST should be deasserted for the corepac.
- ISO_EN should be deasserted to disable the isolation cells.
Corepac enable:
- CLK_EN should be asserted for a few cycles then deasserted while the corepac is still in reset to bring everything to reset values (acknowledge will follow)
- MOD_G_RST should be deasserted to bring the corepac out of reset.
- CLK_EN should be asserted to give the module functional clocks (acknowledge will follow)
- CLKSTOP_REQ should be deasserted (and the acknowledge will follow).
SW_RST_DISABLE:
- Processor is put in idle mode by IDLE instruction.
- Assert CLKSTOP_REQ In corepac (processor will ensure system is idle before responding with acknowledge).
- Deassert CLK_EN to clockgate the corepac (acknowledge will follow).
- Assert MOD_G_RST to put the corepac in reset mode.
Power-down:
- Configure the PDCCMD register to enable power down mode
- Enable CPU interrupt(s) corresponding with wakeup and disable all others
- Execute IDLE instruction
- Assert CLKSTOP_REQ in corepac (processor will ensure system is idle before responding with ack)
Note: C66x DSP Pre-fetch Should Be Disabled before Entering Power Down Mode.
Note: For more information about C66x signals and
registers, see Section 6.4, C66x DSP
Subsystem.
The DSP may hang after multiple iterations of going into C66x Corepac Power-Down and wake up from external events.
The C66x XMC (External Memory Controller) can have outstanding pre-fetch requests when C66x Corepac transitions to a Power Down state. The XMC clocks are gated internally during this transition. While XMC clocks are gated, outstanding pre-fetch request responses are not seen by the XMC which leads to an inconsistent state between the XMC and the L3 Interconnect. When the DSP wakes up, this can manifest as different symptoms within the DSP subsystem, including Cache corruption, incorrect data being returned to the CPU, and can eventually lead to a DSP hang condition.
The steps to avoid this issue are as given below:
- Ensure the code which places the DSP C66x Corepac to Power Down State (power down entry procedure shown below) is placed in the DSP C66x L2 RAM memory.
- Set the IDLE bit in PDCCMD register during initialization.
- Inside the power down entry procedure include the following software sequence:
- Execute MFENCE instruction.
- Write 1 to XPFCMD.INV (address 0x0800_0300).
- Read XPFACS (address 0x0800_0304).
- Execute IDLE instruction.
While executing multi-threaded DSP software with C66x Corepac Power Down caution should be observed to not allow the power down entry sequence to be preempted and switch context.