SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Before initialization, the user should program the FSP-related mode registers (MR1, MR2, MR3, MR11, MR12, MR13, MR14 and MR22) with the relevant values, and the DDRSS_CTL_21[28-24] DFIBUS_FREQ_F2, DDRSS_CTL_21[20-16] DFIBUS_FREQ_F1 and DDRSS_CTL_21[12-8] DFIBUS_FREQ_F0 fields with the frequency set to use. These mode registers are programmed through the following fields:
In addition, the following fields must also be programmed before asserting the DDRSS_CTL_0[0] START bit:
The following bits may or may not be modified, depending on what operations are needed after a frequency change occurs:
Once the DDRSS_CTL_0[0] START bit is asserted, the DDR controller programs the mode registers in the memory devices with these values using the FSP-OP and FSP-WR values from the DDRSS_CTL_180[7-0] MR13_DATA_0 field. Once initialization is complete, either the PHY, PI, or controller will have updated the frequency set points with the needed values.